From 0018037c16961473e73a3e9c1393a8dcf1bb0574 Mon Sep 17 00:00:00 2001 From: Stan Lee Date: Wed, 21 Jan 2026 12:25:28 -0800 Subject: [PATCH] minor changes --- passes/silimate/reg_rename.cc | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/passes/silimate/reg_rename.cc b/passes/silimate/reg_rename.cc index 27a453384..a65f34b06 100644 --- a/passes/silimate/reg_rename.cc +++ b/passes/silimate/reg_rename.cc @@ -116,7 +116,13 @@ struct RegRenamePass : public Pass { if (isMultiBit) { // Index of the register - int index = std::stoi(match[2].str()); + try { + int index = std::stoi(match[2].str()); + } catch (const std::exception &e) { + log_warning("Failed to convert index %s to integer in register %s: %s\n", + match[2].str().c_str(), cell->name.c_str(), e.what()); + continue; + } // Get or create the multi-bit wire Wire *newWire = module->wire(RTLIL::escape_id(baseName)); @@ -134,7 +140,7 @@ struct RegRenamePass : public Pass { // Log that the new wire is being connected to the register log("Connecting register wire %s[%d] to bit %d of %s in module %s\n", - newWire->name.c_str(), index, index, baseName.c_str(), log_id(module)); + newWire->name.c_str(), index, index, log_id(cell), log_id(module)); // Replace all uses of oldWire with newWire[index] auto rewriter = [&](SigSpec &sig) {