2019-02-05 01:46:24 +01:00
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#!/bin/bash
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2019-06-07 20:05:36 +02:00
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set -e
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for aig in *.aig; do
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../../yosys-abc -c "read -c $aig; write ${aig%.*}_ref.v"
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../../yosys -p "
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read_verilog ${aig%.*}_ref.v
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prep
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design -stash gold
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read_aiger -clk_name clock $aig
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prep
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports -seq 16 miter
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"
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2019-02-05 01:46:24 +01:00
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done
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