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yosys/tests/arch/intel_alm/add_sub.ys

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synth_intel_alm: alternative synthesis for Intel FPGAs By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2019-11-19 11:19:00 +01:00
read_verilog ../common/add_sub.v
hierarchy -top top
intel_alm: Add IO buffer insertion Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 15:23:22 +02:00
equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check
synth_intel_alm: alternative synthesis for Intel FPGAs By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2019-11-19 11:19:00 +01:00
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 8 t:MISTRAL_ALUT_ARITH
select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D
intel_alm: add Cyclone 10 GX tests
2020-07-05 19:53:14 +02:00
design -reset
read_verilog ../common/add_sub.v
hierarchy -top top
intel_alm: Add IO buffer insertion Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 15:23:22 +02:00
equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check
intel_alm: add Cyclone 10 GX tests
2020-07-05 19:53:14 +02:00
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 8 t:MISTRAL_ALUT_ARITH
select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D