mirror of https://github.com/YosysHQ/yosys.git
6 lines
169 B
Verilog
6 lines
169 B
Verilog
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// Regression test for bug mentioned in #5160:
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// https://github.com/YosysHQ/yosys/pull/5160#issuecomment-2983643084
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module top;
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initial $display( "\\" );
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endmodule
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