mirror of https://github.com/YosysHQ/yosys.git
14 lines
248 B
Plaintext
14 lines
248 B
Plaintext
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read_verilog -icells <<EOT
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module top(A, B, X, Y);
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input [8:0] A, B;
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output [8:0] X, Y;
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assign X = A + B;
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assign Y = A + B;
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endmodule
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EOT
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select -assert-count 2 t:$add
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equiv_opt -assert opt_merge
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design -load postopt
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select -assert-count 1 t:$add
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