ram block $__MISTRAL_M10K {
    abits 13;
    widths 1 2 5 10 20 40 global; # TODO: per-port width
    cost 128;
    init no_undef;
    # the following is subject to change as more is implemented in nextpnr-mistral
    port sw "W" {
        clock posedge;
        wrtrans "R" old;
    }
    port sr "R" {
        clock posedge;
        rden;
        rdinit zero;
    }
}
