# Default power of two

design -reset

read_rtlil << EOT
autoidx 3
attribute \cells_not_processed 1
attribute \src "<stdin>:1.1-3.10"
module \top
  attribute \src "<stdin>:2.17-2.20"
  wire width 32 $add$<stdin>:2$1_Y
  attribute \src "<stdin>:2.12-2.21"
  wire width 32 signed $pow$<stdin>:2$2_Y
  attribute \src "<stdin>:1.29-1.30"
  wire width 15 input 1 \a
  attribute \src "<stdin>:1.51-1.52"
  wire width 32 output 2 \b
  attribute \src "<stdin>:2.17-2.20"
  cell $add $add$<stdin>:2$1
    parameter \A_SIGNED 0
    parameter \A_WIDTH 15
    parameter \B_SIGNED 0
    parameter \B_WIDTH 32
    parameter \Y_WIDTH 32
    connect \A \a
    connect \B 2
    connect \Y $add$<stdin>:2$1_Y
  end
  attribute \src "<stdin>:2.12-2.21"
  cell $pow $pow$<stdin>:2$2
    parameter \A_SIGNED 0
    parameter \A_WIDTH 32
    parameter \B_SIGNED 0
    parameter \B_WIDTH 32
    parameter \Y_WIDTH 32
    connect \A 2
   connect \B $add$<stdin>:2$1_Y
    connect \Y $pow$<stdin>:2$2_Y
  end
  connect \b $pow$<stdin>:2$2_Y
end
EOT

select -assert-count 1 t:$pow
select -assert-none t:$shl
opt_expr
select -assert-none t:$pow
select -assert-count 1 t:$shl

read_verilog << EOT
module ref(input wire [14:0] a, output wire [31:0] b);
assign b = 1 << (a+2);
endmodule
EOT

equiv_make top ref equiv
select -assert-any -module equiv t:$equiv
equiv_induct
equiv_status -assert

# Other power of 2 value

design -reset

read_verilog <<EOT
module top(input wire [14:0] a, output wire [31:0] b);
assign b = 128**(a+2);
endmodule
EOT

# Check the cell counts have changed correctly
select -assert-count 1 t:$pow
select -assert-none t:$shl
select -assert-none t:$mul
opt_expr
select -assert-none t:$pow
select -assert-count 1 t:$shl
select -assert-count 1 t:$mul

read_verilog <<EOT
module ref(input wire [14:0] a, output wire [31:0] b);
assign b = 1 << (7 * (a+2));
endmodule
EOT

equiv_make top ref equiv
select -assert-any -module equiv t:$equiv
equiv_induct
equiv_status -assert
