read_verilog ../common/adffs.v
design -save read

hierarchy -top adff
proc
equiv_opt -async2sync  -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adff # Constrain all select calls below inside the top module
select -assert-count 1 t:FFCE

select -assert-none t:FFCE %% t:* %D


design -load read
hierarchy -top adffn
proc
equiv_opt -async2sync  -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adffn # Constrain all select calls below inside the top module
select -assert-count 1 t:FFCE
select -assert-count 1 t:LUT1

select -assert-none t:FFCE t:LUT1 %% t:* %D


design -load read
hierarchy -top dffs
proc
equiv_opt -async2sync  -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffs # Constrain all select calls below inside the top module
select -assert-count 1 t:FFRE
select -assert-count 1 t:LUT2
stat
select -assert-none t:FFRE t:LUT2 %% t:* %D


design -load read
hierarchy -top ndffnr
proc
equiv_opt -async2sync  -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd ndffnr # Constrain all select calls below inside the top module
select -assert-count 1 t:FFRE_N
select -assert-count 1 t:LUT1

select -assert-none t:FFRE_N t:LUT1 %% t:* %D
