read_verilog -icells << EOT
module top(...);

input [1:0] D;
input C, R;
output [1:0] Q;

always @(posedge C, posedge R)
  if (R)
    Q <= 0;
  else
    Q <= D;

endmodule
EOT

proc

#equiv_opt -assert -async2sync techmap -map +/adff2dff.v
