read_verilog <<EOF
module top(input [3:0] a, input [3:0] b, output [7:0] y);
	assign y = a * b;
endmodule

module top2(input [7:0] a, input [7:0] b, output [15:0] y);
	assign y = a * b;
endmodule
EOF

synth
timeest
