read_verilog <<EOT
module equiv_add3(
	input [3:0] a, b, c,
	output [3:0] y
);
	assign y = a + b + c;
endmodule
EOT
hierarchy -auto-top
proc
equiv_opt arith_tree
design -load postopt
select -assert-count 1 t:$fa
select -assert-count 1 t:$add
design -reset

read_verilog <<EOT
module equiv_add4(
	input [3:0] a, b, c, d,
	output [3:0] y
);
	assign y = a + b + c + d;
endmodule
EOT
hierarchy -auto-top
proc
equiv_opt arith_tree
design -load postopt
select -assert-count 2 t:$fa
select -assert-count 1 t:$add
design -reset

read_verilog <<EOT
module equiv_add5(
	input [3:0] a, b, c, d, e,
	output [3:0] y
);
	assign y = a + b + c + d + e;
endmodule
EOT
hierarchy -auto-top
proc
equiv_opt arith_tree
design -load postopt
select -assert-count 3 t:$fa
select -assert-count 1 t:$add
design -reset

read_verilog <<EOT
module equiv_add8(
	input [3:0] a, b, c, d, e, f, g, h,
	output [3:0] y
);
	assign y = a + b + c + d + e + f + g + h;
endmodule
EOT
hierarchy -auto-top
proc
equiv_opt arith_tree
design -load postopt
select -assert-count 6 t:$fa
select -assert-count 1 t:$add
design -reset

read_verilog <<EOT
module equiv_signed(
	input signed [3:0] a, b, c, d,
	output signed [5:0] y
);
	assign y = a + b + c + d;
endmodule
EOT
hierarchy -auto-top
proc
equiv_opt arith_tree
design -load postopt
select -assert-count 2 t:$fa
select -assert-count 1 t:$add
design -reset

read_verilog <<EOT
module equiv_mixed(
	input [1:0] a,
	input [3:0] b,
	input [5:0] c,
	output [5:0] y
);
	assign y = a + b + c;
endmodule
EOT
hierarchy -auto-top
proc
equiv_opt arith_tree
design -load postopt
select -assert-count 1 t:$fa
select -assert-count 1 t:$add
design -reset

read_verilog <<EOT
module equiv_sub_3op(
	input [3:0] a, b, c,
	output [3:0] y
);
	assign y = a - b + c;
endmodule
EOT
hierarchy -auto-top
proc
equiv_opt arith_tree
design -load postopt
select -assert-count 2 t:$fa
select -assert-count 1 t:$add
design -reset

read_verilog <<EOT
module equiv_sub_mixed(
	input [3:0] a, b, c, d,
	output [3:0] y
);
	assign y = a + b - c + d;
endmodule
EOT
hierarchy -auto-top
proc
equiv_opt arith_tree
design -load postopt
select -assert-min 1 t:$fa
select -assert-count 1 t:$add
design -reset

read_verilog <<EOT
module equiv_sub_all(
	input [3:0] a, b, c, d,
	output [3:0] y
);
	assign y = a - b - c - d;
endmodule
EOT
hierarchy -auto-top
proc
equiv_opt arith_tree
design -load postopt
select -assert-min 1 t:$fa
select -assert-count 1 t:$add
design -reset

read_verilog <<EOT
module equiv_sub_signed(
	input signed [3:0] a, b, c, d,
	output signed [5:0] y
);
	assign y = a + b - c - d;
endmodule
EOT
hierarchy -auto-top
proc
equiv_opt arith_tree
design -load postopt
select -assert-count 3 t:$fa
select -assert-count 1 t:$add
design -reset

read_verilog <<EOT
module equiv_double_neg(
	input [3:0] a, b, c,
	output [3:0] y
);
	wire [3:0] ab = a - b;
	assign y = c - ab;
endmodule
EOT
hierarchy -auto-top
proc
equiv_opt arith_tree
design -load postopt
select -assert-count 2 t:$fa
select -assert-count 1 t:$add
design -reset
