read_verilog ../common/logic.v
hierarchy -top top
proc
equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 8 t:LUT4
select -assert-none t:LUT4 t:INV t:IB t:OB t:VLO t:VHI %% t:* %D
