read_verilog ../common/shifter.v
hierarchy -top top
proc
flatten
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module

select -assert-count 8 t:FACADE_FF
select -assert-none t:FACADE_FF t:FACADE_IO %% t:* %D
