read_verilog ../common/latches.v
design -save read

hierarchy -top latchp
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_quicklogic
cd latchp # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT3
select -assert-count 3 t:inpad
select -assert-count 1 t:outpad

select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D


design -load read
hierarchy -top latchn
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_quicklogic
cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT3
select -assert-count 3 t:inpad
select -assert-count 1 t:outpad

select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D


design -load read
hierarchy -top latchsr
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_quicklogic
cd latchsr # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT2
select -assert-count 1 t:LUT4
select -assert-count 5 t:inpad
select -assert-count 1 t:outpad

select -assert-none t:LUT2 t:LUT4 t:inpad t:outpad %% t:* %D
