read_verilog <<EOT
module top(...);

input [7:0] wa;
input [7:0] ra1;
input [7:0] ra2;
input [7:0] wd;
input clk;
wire [7:0] rd1;
wire [7:0] rd2;

reg [7:0] mem[0:7];

always @(posedge clk)
	mem[wa] <= wd;
assign rd1 = mem[ra1];
assign rd2 = mem[ra2];

initial mem[8'h12] = 8'h34;

endmodule
EOT

proc

select -assert-count 2 t:$memrd
select -assert-count 1 t:$memwr_v2
select -assert-count 1 t:$meminit_v2
design -save orig

opt_clean
select -assert-none t:$memrd
select -assert-none t:$memwr_v2
select -assert-none t:$meminit_v2

design -load orig
expose top/rd1
opt_clean
select -assert-count 1 t:$memrd
select -assert-count 1 t:$memwr_v2
select -assert-count 1 t:$meminit_v2

design -load orig
expose top/rd1 top/rd2
opt_clean
select -assert-count 2 t:$memrd
select -assert-count 1 t:$memwr_v2
select -assert-count 1 t:$meminit_v2
