read_verilog <<EOT

module xilinx_srl_static_test(input i, clk, output [1:0] q);
reg head = 1'b0;
reg [3:0] shift1 = 4'b0000;
reg [3:0] shift2 = 4'b0000;

always @(posedge clk) begin
    head <= i;
    shift1 <= {shift1[2:0], head};
    shift2 <= {shift2[2:0], head};
end

assign q = {shift2[3], shift1[3]};
endmodule

EOT

design -save read

hierarchy -top xilinx_srl_static_test
proc
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
equiv_opt -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd xilinx_srl_static_test # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:SRL16E
select -assert-none t:BUFG t:SRL16E %% t:* %D

design -load read
hierarchy -top xilinx_srl_static_test
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nosrl -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd xilinx_srl_static_test # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 5 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
