read_verilog ../../common/dffs.v
rename dff my_dff # Work around conflicting module names between test and vendor cells
rename dffe my_dffe
design -save read

hierarchy -top my_dff
proc
equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd my_dff # Constrain all select calls below inside the top module
select -assert-count 1 t:ckpad
select -assert-count 1 t:dffepc
select -assert-count 1 t:inpad
select -assert-count 1 t:logic_0
select -assert-count 1 t:logic_1
select -assert-count 1 t:outpad

select -assert-none t:ckpad t:dffepc t:inpad t:logic_0 t:logic_1 t:outpad %% t:* %D

design -load read
hierarchy -top my_dffe
proc
equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd my_dffe # Constrain all select calls below inside the top module

select -assert-count 1 t:ckpad
select -assert-count 1 t:dffepc
select -assert-count 2 t:inpad
select -assert-count 1 t:logic_0
select -assert-count 1 t:outpad

select -assert-none t:ckpad t:dffepc t:inpad t:logic_0 t:outpad %% t:* %D
