read_verilog ../common/counter.v
hierarchy -top top
proc
flatten
equiv_opt -assert -multiclock -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module

select -assert-count 1 t:EFX_GBUFCE
select -assert-count 8 t:EFX_FF
select -assert-count 9 t:EFX_ADD
select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_ADD %% t:* %D
