read_verilog ../common/fsm.v
hierarchy -top fsm
proc
flatten

equiv_opt -run :prove -map +/gatemate/cells_sim.v synth_gatemate -noiopad
async2sync
miter -equiv -make_assert -flatten gold gate miter
stat
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter

design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module

select -assert-count 1 t:CC_BUFG
select -assert-count 6 t:CC_DFF
select -assert-max 5 t:CC_LUT2
select -assert-max 6 t:CC_LUT3
select -assert-max 9 t:CC_LUT4
select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 t:CC_LUT3 t:CC_LUT4 %% t:* %D
