read_verilog ../common/logic.v
hierarchy -top top
proc
equiv_opt -assert -map +/fabulous/prims.v synth_fabulous # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-max 1 t:LUT1
select -assert-max 6 t:LUT2
select -assert-max 2 t:LUT4
select -assert-none t:LUT1 t:LUT2 t:LUT4 %% t:* %D
