read_verilog ../common/logic.v
hierarchy -top top
proc
equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module

select -assert-count 9 t:NX_LUT
select -assert-none t:NX_LUT %% t:* %D
