read_verilog <<EOT
module add8(
	input [15:0] a, b, c, d, e, f, g, h,
	output [15:0] y
);
	assign y = a + b + c + d + e + f + g + h;
endmodule
EOT
hierarchy -auto-top
proc

arith_tree
select -assert-count 6 t:$fa
select -assert-count 1 t:$add

arith_tree
select -assert-count 6 t:$fa
select -assert-count 1 t:$add
select -assert-none t:$sub
design -reset

read_verilog <<EOT
module macc_idempotent(
	input [15:0] a, b, c, d, e, f, g, h,
	output [15:0] y
);
	assign y = a + b + c + d + e + f + g + h;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt_clean

arith_tree
select -assert-count 6 t:$fa
select -assert-count 1 t:$add
select -assert-none t:$sub
select -assert-none t:$alu

arith_tree
select -assert-count 6 t:$fa
select -assert-count 1 t:$add
select -assert-none t:$sub
select -assert-none t:$alu
design -reset
