read_verilog ../common/add_sub.v
hierarchy -top top
proc
design -save orig

equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 10 t:LUT4
select -assert-none t:IB t:OB t:VLO t:LUT4 %% t:* %D

design -load orig

equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus -abc9 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 7 t:LUT4
select -assert-count 2 t:WIDEFN9
select -assert-none t:IB t:OB t:VLO t:LUT4 t:WIDEFN9 %% t:* %D
