# Generated by Yosys 0.45+139 (git sha1 e7fc1b0cc, g++ 13.2.0 -fPIC -O3)
autoidx 2
attribute \architecture "Behavioral"
attribute \library "work"
attribute \hdlname "vector_assign"
attribute \src "tests/verific/vector_assign.vhd:4.8-4.21"
module \vector_assign
  attribute \src "tests/verific/vector_assign.vhd:6.9-6.10"
  wire width 4 input 2 \a
  attribute \src "tests/verific/vector_assign.vhd:7.9-7.10"
  wire width 4 output 1 \b
  attribute \src "tests/verific/vector_assign.vhd:13.5-13.6"
  cell $pos $verific$buf_3$tests/verific/vector_assign.vhd:13$1
    parameter \A_SIGNED 0
    parameter \A_WIDTH 4
    parameter \Y_WIDTH 4
    connect \A \a
    connect \Y \b
  end
end
