design -reset
read_verilog ../common/lutram.v
hierarchy -top lutram_1w1r -chparam A_WIDTH 5
proc
memory -nomap
equiv_opt -run :prove -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad
memory
opt -full

miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter

design -load postopt
cd lutram_1w1r
select -assert-count 8 t:FFRE
select -assert-count 8 t:RAMS64X1
select -assert-none t:FFRE t:RAMS64X1 %% t:* %D


design -reset
read_verilog ../common/lutram.v
hierarchy -top lutram_1w1r
proc
memory -nomap
equiv_opt -run :prove -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad
memory
opt -full

miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter

design -load postopt
cd lutram_1w1r
dump
select -assert-count 8 t:FFRE
select -assert-count 8 t:RAMS64X1
select -assert-none t:FFRE t:RAMS64X1 %% t:* %D


design -reset
read_verilog ../common/lutram.v
hierarchy -top lutram_1w3r
proc
memory -nomap
equiv_opt -run :prove -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad
memory
opt -full

miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter

design -load postopt
cd lutram_1w3r
select -assert-count 24 t:FFRE
select -assert-count 16 t:RAMD32X1
select -assert-none t:FFRE t:RAMD32X1 %% t:* %D


design -reset
read_verilog ../common/lutram.v
hierarchy -top lutram_1w3r -chparam A_WIDTH 6
proc
memory -nomap
equiv_opt -run :prove -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad
memory
opt -full

miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter

design -load postopt
cd lutram_1w3r
select -assert-count 24 t:FFRE
select -assert-count 16 t:RAMD64X1
select -assert-none t:FFRE t:RAMD64X1 %% t:* %D


design -reset
read_verilog ../common/lutram.v
hierarchy -top lutram_1w1r -chparam A_WIDTH 5 -chparam D_WIDTH 6
proc
memory -nomap
equiv_opt -run :prove -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad
memory
opt -full

miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter

design -load postopt
cd lutram_1w1r
select -assert-count 6 t:FFRE
select -assert-count 6 t:RAMS64X1
select -assert-none t:FFRE t:RAMS64X1 %% t:* %D


design -reset
read_verilog ../common/lutram.v
hierarchy -top lutram_1w1r -chparam A_WIDTH 6 -chparam D_WIDTH 6
proc
memory -nomap
equiv_opt -run :prove -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad
memory
opt -full

miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter

design -load postopt
cd lutram_1w1r
select -assert-count 6 t:FFRE
select -assert-count 6 t:RAMS64X1
select -assert-none t:FFRE t:RAMS64X1 %% t:* %D
