diff --git a/Draw-compact-testbenches-in-xschem.md b/Draw-compact-testbenches-in-xschem.md
new file mode 100644
index 0000000..3f950f0
--- /dev/null
+++ b/Draw-compact-testbenches-in-xschem.md
@@ -0,0 +1,29 @@
+Xschem is targeted for VLSI design, and as such it is built around the concept of vector nets, vector ports and vector instances.  
+A simple example of a vectored instance wired with vector nets is shown below:
+
+![1](https://github.com/StefanSchippers/xschem/assets/69359491/d1efe8a6-1046-4744-a2be-4e73327a73e1)
+
+This simple placement is equivalent to placing 32 single `xrdec[31]`, `xrdec[30]`, ..., `xrdec[0]` blocks.  
+If you look at the `LDWL[511:0]` net it represents a bus of 512 wires. Wires `LDWL[511:496]` will be connected to instance xrdec[31], wires `LDWL[495:480]` will be connected to `xrdec[30]` and so on.
+
+See this design where 16 blocks are all wired manually to wide buses:
+
+![1](https://github.com/StefanSchippers/xschem/assets/69359491/4d4d8631-69b0-4bcd-afec-d22eaac75c90)
+
+The same design can be expressed in this compact form. 
+
+![2](https://github.com/StefanSchippers/xschem/assets/69359491/dc534ae5-8952-4ed0-a0bd-1e2b7f453c86)
+
+This compact form is way easier to draw and less prone to typos.
+just as a note the notation `x[60:0:4]` means a bundle of the following bits: `x[60], x[56], x[52], ..., x[0]`.
+The leftmost instance (`x1[15]` in the example below) connects to the leftmost bits of the bus, that is:
+```
+                              x115
+         ----------------------
+        |                      |
+x[60] --| x[0]                 |
+        |                      |
+         ----------------------
+```
+
+For more info on bus  / vector notation see the [manual page](https://xschem.sourceforge.io/stefan/xschem_man/tutorial_busses.html).