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adc_bridge.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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ammeter.sym
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better text positioning (net_name) on some devices/ symbols
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2020-10-17 01:07:18 +02:00 |
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arch_declarations.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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architecture.sym
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replaced @ character with ? for spice netlist node multiplicity tags, so translate() will not try to expand them, do not print erc warnings for "non electrical" symbols (architecture, package, port_attributes, use, etc), print_spice_element() result string will be forwarded to translate() if enclosed within tcleval(...), so all @vars will be expanded. translate() in turn will forward to tcl_hook() if necessary.
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2020-10-14 23:15:05 +02:00 |
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asrc.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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assign.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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attributes.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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bsource.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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bus_connect.sym
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devices/ symbol fixes
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2020-10-06 03:20:56 +02:00 |
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bus_connect_nolab.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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capa-2.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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capa.sym
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better text positioning (net_name) on some devices/ symbols
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2020-10-17 01:07:18 +02:00 |
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cccs.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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ccvs.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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code.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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code_shown.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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conn_3x1.sym
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allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example
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2020-11-24 02:54:45 +01:00 |
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conn_4x1.sym
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removed some redundant calls in prepare_netlist_structs(), no full instance spatial rehash if adding a component, set template name initials for components in devices/ that do not map directly to spice elements to lowercase letters.
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2020-10-18 23:58:40 +02:00 |
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conn_8x1.sym
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allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example
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2020-11-24 02:54:45 +01:00 |
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conn_10x2.sym
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removed some redundant calls in prepare_netlist_structs(), no full instance spatial rehash if adding a component, set template name initials for components in devices/ that do not map directly to spice elements to lowercase letters.
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2020-10-18 23:58:40 +02:00 |
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conn_14x1.sym
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removed some redundant calls in prepare_netlist_structs(), no full instance spatial rehash if adding a component, set template name initials for components in devices/ that do not map directly to spice elements to lowercase letters.
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2020-10-18 23:58:40 +02:00 |
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connect.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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connector.sym
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removed some redundant calls in prepare_netlist_structs(), no full instance spatial rehash if adding a component, set template name initials for components in devices/ that do not map directly to spice elements to lowercase letters.
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2020-10-18 23:58:40 +02:00 |
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crystal-2.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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crystal.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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dac_bridge.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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delay.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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delay_line.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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diode.sym
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allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example
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2020-11-24 02:54:45 +01:00 |
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flash_cell.sym
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removed some redundant calls in prepare_netlist_structs(), no full instance spatial rehash if adding a component, set template name initials for components in devices/ that do not map directly to spice elements to lowercase letters.
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2020-10-18 23:58:40 +02:00 |
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generic_pin.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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gnd.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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ind.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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iopin.sym
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slight resize in pin text size for better look. top frame in insert text dialog does not extend vertically.
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2020-10-11 01:38:28 +02:00 |
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ipin.sym
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slight resize in pin text size for better look. top frame in insert text dialog does not extend vertically.
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2020-10-11 01:38:28 +02:00 |
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isource.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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isource_arith.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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isource_pwl.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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isource_table.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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jumper.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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k.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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lab_generic.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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lab_pin.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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lab_show.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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lab_wire.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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launcher.sym
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xschem setprop made way faster if "fast" argument is provided. Example "clear probes" launcher object in mos_power_ampli.sch.
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2020-10-19 02:07:17 +02:00 |
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led.sym
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allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example
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2020-11-24 02:54:45 +01:00 |
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netlist.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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netlist_at_end.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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netlist_not_shown.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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netlist_not_shown_at_end.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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netlist_options.sym
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allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example
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2020-11-24 02:54:45 +01:00 |
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ngspice_get_expr.sym
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Option (default now) to export svg images using the svg <text> element. This makes generated SVGs much smaller and in most cases faster to render.
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2020-11-18 18:29:14 +01:00 |
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ngspice_get_value.sym
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exampels/poweramp.sch and examples/cmos_example.sch show how to use dynamuc ngspice simulation data backannotation, optimized fix of previous bbox bug
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2020-10-20 19:48:59 +02:00 |
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ngspice_probe.sym
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exampels/poweramp.sch and examples/cmos_example.sch show how to use dynamuc ngspice simulation data backannotation, optimized fix of previous bbox bug
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2020-10-20 19:48:59 +02:00 |
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nmos-sub.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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nmos.sym
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allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example
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2020-11-24 02:54:45 +01:00 |
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nmos3.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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nmos4.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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noconn.sym
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optimize unselect_all()
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2020-09-30 02:53:20 +02:00 |
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npn.sym
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allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example
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2020-11-24 02:54:45 +01:00 |
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opin.sym
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slight resize in pin text size for better look. top frame in insert text dialog does not extend vertically.
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2020-10-11 01:38:28 +02:00 |
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package.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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package_not_shown.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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param.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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param_agauss.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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parax_cap.sym
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devices/ symbol fixes
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2020-10-06 03:20:56 +02:00 |
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pmos-sub.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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pmos.sym
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allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example
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2020-11-24 02:54:45 +01:00 |
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pmos3.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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pmos4.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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pmoshv4.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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pmosnat.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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pnp.sym
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allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example
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2020-11-24 02:54:45 +01:00 |
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port_attributes.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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res.sym
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allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example
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2020-11-24 02:54:45 +01:00 |
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res_ac.sym
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added res_ac.sym
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2020-11-06 19:43:26 +01:00 |
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rgb_led.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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spice_probe.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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spice_probe_vdiff.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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sqwsource.sym
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sqwsource: do not use tcleval, leave the simple expressions parsing to the simulator
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2020-10-26 02:58:29 +01:00 |
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switch.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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switch_ngspice.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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switch_v_xyce.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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title-2.sym
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NumLock and CapsLock check for windows
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2020-09-22 21:02:51 +02:00 |
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title.sym
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LICENSE cosmetic editing
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2020-10-10 11:49:12 +02:00 |
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use.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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var_res.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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vccs.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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vcr.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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vcvs.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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vdd.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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verilog_delay.sch
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verilog_preprocessor and verilog_timescale now use verilog_format instead of format (which is for spice), corrected verilog_netlist.c; better backslash and quote (") escaping and unescaping when using attribute select combobox; for unquoting use "xschem get_tok tok 2" instead of "xschem get_tok tok 0" + regsub ....(remove backslashes)...
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2020-10-10 23:21:23 +02:00 |
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verilog_delay.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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verilog_preprocessor.sym
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verilog_preprocessor and verilog_timescale now use verilog_format instead of format (which is for spice), corrected verilog_netlist.c; better backslash and quote (") escaping and unescaping when using attribute select combobox; for unquoting use "xschem get_tok tok 2" instead of "xschem get_tok tok 0" + regsub ....(remove backslashes)...
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2020-10-10 23:21:23 +02:00 |
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verilog_timescale.sym
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more consistent get_tok_value() regarding escaping
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2020-11-29 01:59:17 +01:00 |
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vsource.sym
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better text positioning (net_name) on some devices/ symbols
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2020-10-17 01:07:18 +02:00 |
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vsource_arith.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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vsource_pwl.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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zener.sym
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allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example
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2020-11-24 02:54:45 +01:00 |
eb2d143e77