52 lines
1.9 KiB
Plaintext
52 lines
1.9 KiB
Plaintext
v {xschem version=3.4.5 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {type=logo
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template="name=l1 author=\\"Stefan Schippers\\" rev=1.0 lock=false"
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verilog_ignore=true
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vhdl_ignore=true
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spice_ignore=true
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tedax_ignore=true
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}
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V {}
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S {}
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E {}
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L 4 385 0 2500 0 {}
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L 4 0 0 65 0 {}
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L 4 2500 -1770 2500 0 {}
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L 4 0 -1770 2500 -1770 {}
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L 4 0 -1770 0 0 {}
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L 4 1180 -160 1180 0 {}
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L 4 1180 -160 2500 -160 {}
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L 4 1180 -80 2500 -80 {}
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L 4 1810 -80 1810 0 {}
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L 4 1810 -160 1810 -80 {}
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L 4 1520 -80 1520 0 {}
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P 5 38 140 -15 135 -10 125 0 135 10 147.5 22.5 155 30 147.5 30 140 30 135 30 130 25 125 20 115 10 105 20 100 25 95 30 90 30 82.5 30 75 30 82.5 22.5 95 10 105 0 95 -10 82.5 -22.5 75 -30 82.5 -30 90 -30 95 -30 100 -25 105 -20 115 -10 125 -20 130 -25 135 -30 140 -30 147.5 -30 155 -30 147.5 -22.5 140 -15 {fill=true
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bezier=1}
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T {@time_last_modified} 1820 -60 0 0 0.8 0.8 {}
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T {@author} 1190 -140 0 0 0.8 0.8 {}
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T {Page @page of @pages} 1190 -60 0 0 0.8 0.8 {}
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T {@title} 1820 -120 0 0 0.6 0.6 {vcenter=true}
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T {Rev. @rev} 1530 -60 0 0 0.8 0.8 {}
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T {SCHEM} 155 -25 0 0 1 1 {}
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