132 lines
5.0 KiB
HTML
132 lines
5.0 KiB
HTML
<!DOCTYPE html>
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<html>
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<head>
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<title>NETLISTING</title>
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<link rel="stylesheet" type="text/css" href="xschem_man.css" />
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<style type="text/css">
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/* Local styling goes here */
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p{padding: 15px 30px 10px;}
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</style>
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</head>
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<body>
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<!-- start of slide -->
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<div class="content">
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<!-- slide title -->
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<h1>NETLISTING</h1><br>
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<p>
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XSCHEM has 3 predefined netlisting modes, <kbd>Spice</kbd>, <kbd>Verilog</kbd> and
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<kbd>VHDL</kbd>. Netlisting mode can be set in the <kbd>Options</kbd> menu
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(<kbd>Vhdl</kbd>, <kbd>Verilog</kbd> <kbd>Spice</kbd> radio buttons)
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or with the <kbd><Shift>V</kbd> key. Once a netlist mode is set, hitting the
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<kbd>Netlist</kbd> button on the top-right of the menu bar or the <kbd><Shift>N</kbd>
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key will produce the netlist file in the defined simulation directory.
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The simulation directory is one important path that is specified in the <kbd>xschemrc</kbd>
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file, if no one is defined XSCHEM will prompt for a directory.
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The path where netlists are produced can be changed with the
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<kbd>Simulation->Set netlist dir</kbd> menu entry.
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The netlist filename is <kbd>cellname.ext</kbd> where <kbd>cellname</kbd> is the name of the
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top-level schematic from which the netlist has been generated, and <kbd>ext</kbd> is the
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file extension:</p>
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<ul>
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<li><kbd>spice</kbd> for spice netlist.</li>
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<li><kbd>vhdl</kbd> for vhdl netlist.</li>
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<li><kbd>v</kbd> for verilog netlist.</li>
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</ul>
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<h3> EXAMPLE</h3>
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<p>
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Consider the following top level schematic, part of the XSCHEM distribution
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(<kbd>examples/poweramp.sch</kbd>).</p>
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<img src="netlisting1.png">
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<p>
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This schematic is made of some <kbd>leaf</kbd> components and some
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<kbd>subcircuit</kbd> components:
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</p>
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<ul>
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<li><kbd>leaf</kbd>: these componens are 'known' to the simulator,
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netlist of these blocks is done by specifying a 'format' attribute in the symbol
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property string. Examples of leaf components in the schematic above are voltage sources,
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resistors, capacitors, dependent sources. The following are examples of leaf component
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instantiations in a SPICE netlist:<br><br>
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<pre class="code">
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c3 VSS VNN 100u m=1
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r11 VPP net1 0.3 m=1
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r9 VNN net2 0.3 m=1
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r19 OUTM FBN '100k' m=1
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</pre><br>
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The format of resistor (and capacitor) SPICE netlist is defined in the
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format attribute of the symbol global property: <br><br>
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<pre class="code">
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format="@name @pinlist @value m=@m"</pre>
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</li><br>
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<li><kbd>subcircuit</kbd>: these components are not base blocks known to the simulator, but
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are representation of a more complex block. These components have in addition to the symbol
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a schematic representation. In the picture example the <kbd>mos_power_ampli</kbd> is a
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subcircuit block. These type of components also have a 'format' property that defines
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a subcircuit call. A subcircuit call specifies the connections of nets to the symbol pins
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and the symbol name. The following two subcircuit calls are present in the SPICE
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netlist:<br><br>
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<pre class="code">
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x1 OUTM VSSX FBN VPP VNN VSS mos_power_ampli
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x0 OUTP INX FB VPP VNN VSS mos_power_ampli</pre>
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<br>
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The format of subcircuit type components is also defined in the symbol <kbd>format</kbd>
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attribute: <br><br>
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<pre class="code">
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format="@name @pinlist @symname"</pre>
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</li>
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</ul>
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<p>
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For subcircuits, after completing the netlist of the top level the XSCHEM' netlister
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will recursively generate all the netlists of subcircuit components until leaf
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schematics are reached that do not instantiate further subcircuits.
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</p>
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<pre class="code">
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...
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... (end of top level netlist)
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...
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* expanding symbol: examples/mos_power_ampli # of pins=6
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.subckt mos_power_ampli OUT PLUS MINUS VPP VNN VSS
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*.ipin PLUS
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*.ipin MINUS
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*.ipin VPP
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...
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... </pre>
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<br>
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<h3> Other netlist formats</h3>
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<p>
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All the concepts explained for SPICE netlist apply for Verilog and VHDL formats.
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Its up to the designer to ensure that the objects in the schematic are 'known' to the
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target simulator. For example a resistor is normally
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not used in VHDL or Verilog designs, so unless an appropriate 'format'
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attribute is defined (for example a <kbd>rtran</kbd> device may be good for a verilog
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resistor with some limitations).
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The format attribute for Verilog is called <kbd>verilog_format</kbd> and
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the attribute for VHDL is <kbd>vhdl_format</kbd><br>
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The following example shows two attributes in a NMOS symbol that define the format
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for SPICE and for Verilog and some valid default (<kbd>template</kbd>) values:
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</p>
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<pre class="code">
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type=nmos
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format="@name @pinlist @model w=@w l=@l m=@m"
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verilog_format="@verilog_gate #(@del ) @name ( @@d , @@s , @@g );"
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template="name=x1 verilog_gate=nmos del=50,50,50 model=NCH w=0.68 l=0.07 m=1"
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generic_type="model=string" </pre>
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<br>
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