142 lines
4.3 KiB
XML
142 lines
4.3 KiB
XML
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {
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-- process
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-- variable t : time;
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-- variable C : rreal;
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-- begin
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-- wait on A'transaction , B'transaction , ENAB'transaction until t /= now;
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-- t := now;
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--
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-- A<=rreal'(0.0,0.0,0.0);
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-- B<=rreal'(0.0,0.0,0.0);
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-- for i in 1 to 6 loop
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-- wait for 0 ns;
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-- end loop;
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--
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-- if ENAB = '1' then
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-- for i in 1 to 6 loop
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-- C := resolved_real( (A, B) );
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-- B <= C;
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-- A <= C;
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-- wait for 0 ns;
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-- end loop;
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-- end if;
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--
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-- end process;
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process
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variable last : time;
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variable aa,bb : rreal;
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begin
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wait until ( SCHEDULE'transaction'event or A'event or B'event or ENAB'event ) and now>last;
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last := now;
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print(switch_rreal'PATH_NAME & " start switch process: " & time'image(now) );
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if now= 0 ns then
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aa:=rreal'(0.0,0.0,0.0);
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bb:=rreal'(0.0,0.0,0.0);
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A <= aa ;
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B <= bb ;
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elsif ENAB'event and ENAB='1' then SCHEDULE <= 4 after del;
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elsif ENAB'event and ENAB='0' then SCHEDULE <= 3 after del;
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elsif B'event and ENAB='1' then SCHEDULE <= 2 after del;
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elsif A'event and ENAB='1' then SCHEDULE <= 1 after del;
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elsif SCHEDULE'transaction'event and SCHEDULE=3 then -- ENAB=0 event
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print(switch_rreal'PATH_NAME & " release outputs: " & time'image(now) );
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aa:=rreal'(0.0,0.0,0.0);
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bb:=rreal'(0.0,0.0,0.0);
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A <= aa ;
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B <= bb ;
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elsif SCHEDULE'transaction'event and SCHEDULE=4 then -- ENAB=1 event
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aa := B;
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bb := A;
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A <= aa ;
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print(switch_rreal'PATH_NAME & " enab forcing A, done: " & time'image(now) );
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print2(A);
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B <= bb ;
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print(switch_rreal'PATH_NAME & " enab forcing B, done: " & time'image(now) );
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print2(B);
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elsif SCHEDULE'transaction'event and SCHEDULE=2 then -- B event
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print(switch_rreal'PATH_NAME & " B'event: " & time'image(now) );
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aa.conduct := B.conduct - bb.conduct;
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aa.cap := B.cap - bb.cap;
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if aa.conduct /= 0.0 then
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aa.value := ( B.value * B.conduct - bb.value * bb.conduct) / aa.conduct;
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else
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aa.value := B.value;
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end if;
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A <= aa ;
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elsif SCHEDULE'transaction'event and SCHEDULE=1 then -- A event
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print(switch_rreal'PATH_NAME & " A'event: " & time'image(now) );
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bb.conduct := A.conduct - aa.conduct;
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bb.cap := A.cap - aa.cap;
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if bb.conduct /= 0.0 then
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bb.value := ( A.value * A.conduct - aa.value * aa.conduct) / bb.conduct;
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else
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bb.value := A.value;
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end if;
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B <= bb ;
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end if; -- now = 0
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end process;
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}
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K {type=subcircuit
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format="@name @pinlist @symname"
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template="name=x1 del=\\"2 ns\\""
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generic_type="del=time"}
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V {}
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S {}
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E {}
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L 4 -110 -20 110 -20 {}
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L 4 -110 20 110 20 {}
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L 4 -110 -20 -110 20 {}
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L 4 110 -20 110 20 {}
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L 4 110 -10 150 -10 {}
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L 4 -150 -10 -110 -10 {}
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L 4 -150 10 -110 10 {}
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T {@symname} -49.5 -6 0 0 0.3 0.3 {}
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T {@name} 65 -32 0 0 0.2 0.2 {}
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C {ipin.sym} -150 10 0 0 {name=p3 lab=ENAB}
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C {iopin.sym} -150 -10 0 1 {name=p2 lab=A sig_type=rreal}
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C {arch_declarations.sym} 140 -160 0 0 {
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signal SCHEDULE : integer ;
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procedure print2( signal x : in rreal) is
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begin
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print(" " & x'SIMPLE_NAME & ".value=" & real'image(x.value)& " t= " & time'image(now) );
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print(" " & x'SIMPLE_NAME & ".cap=" & real'image(x.cap) & " t= " & time'image(now));
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print(" " & x'SIMPLE_NAME & ".conduct=" & real'image(x.conduct) & " t= " & time'image(now));
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end print2;
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}
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C {iopin.sym} 150 -10 0 0 {name=p1 lab=B sig_type=rreal}
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C {use.sym} -130 -260 0 0 {library ieee;
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use std.TEXTIO.all;
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use ieee.std_logic_1164.all;
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library work;
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use work.rrreal_pkg.all;
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}
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