60 lines
2.3 KiB
XML
60 lines
2.3 KiB
XML
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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V {}
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S {}
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E {}
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N 160 -310 250 -310 {lab=A}
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N 160 -190 210 -190 {lab=B}
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N 440 -380 500 -380 {lab=Z}
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N 440 -500 440 -470 {lab=VCC}
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N 290 -500 440 -500 {lab=VCC}
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N 290 -500 290 -470 {lab=VCC}
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N 290 -160 290 -130 {lab=VSS}
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N 180 -110 290 -110 {lab=VSS}
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N 290 -130 290 -110 {lab=VSS}
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N 180 -500 290 -500 {lab=VCC}
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N 290 -280 290 -220 {lab=#net1}
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N 290 -410 290 -340 {lab=Z}
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N 290 -380 440 -380 {lab=Z}
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N 440 -410 440 -380 {lab=Z}
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N 210 -190 250 -190 {lab=B}
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N 400 -440 400 -400 {lab=A}
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N 240 -400 400 -400 {lab=A}
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N 240 -400 240 -310 {lab=A}
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N 210 -440 210 -190 {lab=B}
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N 210 -440 250 -440 {lab=B}
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C {ipin.sym} 160 -310 0 0 {name=p1 lab=A}
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C {opin.sym} 500 -380 0 0 {name=p2 lab=Z}
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C {ipin.sym} 160 -190 0 0 {name=p3 lab=B}
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C {title.sym} 160 -30 0 0 {name=l7 author="Stefan Schippers"}
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C {gnd.sym} 180 -110 0 0 {name=l2 lab=VSS}
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C {vdd.sym} 180 -500 0 0 {name=l1 lab=VCC}
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C {lab_pin.sym} 290 -310 0 1 {name=l3 sig_type=std_logic lab=VSS}
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C {lab_pin.sym} 290 -190 0 1 {name=l4 sig_type=std_logic lab=VSS}
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C {lab_pin.sym} 290 -440 0 1 {name=l5 sig_type=std_logic lab=VCC}
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C {lab_pin.sym} 440 -440 0 1 {name=l6 sig_type=std_logic lab=VCC}
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C {nmos4.sym} 270 -310 0 0 {name=m1 model=CMOSN w=WN l=LLN m=1}
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C {nmos4.sym} 270 -190 0 0 {name=m1 model=CMOSN w=WN l=LLN m=1}
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C {pmos4.sym} 270 -440 0 0 {name=m2 model=CMOSP w=WP l=LP m=1}
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C {pmos4.sym} 420 -440 0 0 {name=m2 model=CMOSP w=WP l=LP m=1}
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