53 lines
1.8 KiB
XML
53 lines
1.8 KiB
XML
v {xschem version=3.4.5 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {}
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V {}
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S {}
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E {}
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N 360 -240 400 -240 {
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lab=CK}
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N 210 -190 400 -190 {
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lab=B}
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N 210 -280 400 -280 {
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lab=A[3:0]}
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N 540 -280 580 -280 {
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lab=Z,NC1,NC2,NC3}
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N 330 -150 470 -150 {
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lab=RST}
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N 470 -210 470 -150 {
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lab=RST}
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C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
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C {ipin.sym} 210 -280 0 0 {name=p1 lab=A[3:0]}
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C {ipin.sym} 210 -190 0 0 {name=p3 lab=B}
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C {opin.sym} 810 -250 0 0 {name=p4 lab=Z}
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C {ipin.sym} 330 -150 0 0 {name=p5 lab=RST}
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C {ipin.sym} 360 -240 0 0 {name=p7 lab=CK}
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C {use.sym} 380 -480 0 0 {------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;}
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C {lab_pin.sym} 580 -280 0 1 {name=l2 sig_type=std_logic lab=Z,NC1,NC2,NC3}
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C {latch.sym} 470 -260 0 0 {name=x2[3:0] delay="200 ps" del=200}
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C {lab_pin.sym} 540 -240 0 1 {name=l3 sig_type=std_logic lab=NC4,NC5,NC6,NC7}
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C {noconn.sym} 400 -190 2 0 {name=l4}
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