v {xschem version=3.1.0 file_version=1.2 } G {} K {} V {// these are the stimulus parameters // and are *NOT* the spec minimum/maximum values // spec minimum/maximum values for timing checks are // in the "timing check' section of module 'lpddr' integer tis = 200; // 2ns... to be adjusted to reflect real spec data integer tih = 200; integer tck=1000; integer tds=100; integer tdh=100; integer tdqss; integer twpre; integer twpst; initial begin tdqss=tck*5/4; twpre = tck/4; twpst = tck/2; end integer i,j; integer wpst; integer wpre; integer tmp_wpst; integer ndata, tmp_ndata; integer data[511:0]; integer lmask[15:0], umask[15:0]; reg write_bus_cycles=0; reg [1:0] iDQS_PAD = 2'bzz; reg [15:0] iDQ_PAD='hz; task init; begin CKE_PAD=0; BA_PAD='bz; APAD='bz; CEN_PAD=1; WEN_PAD=1'bz; RASN_PAD=1'bz; CASN_PAD=1'bz; DM_PAD='hz; #tis; CK_PAD=0; CKN_PAD=1; #(tck/2); CK_PAD=0; CKN_PAD=1; #(tck/2-tis); end endtask task deselect; begin CKE_PAD=1; BA_PAD='bz; APAD='bz; CEN_PAD=1; WEN_PAD=1'bz; RASN_PAD=1'bz; CASN_PAD=1'bz; #tis; CK_PAD=1; CKN_PAD=0; #tih; CEN_PAD=1'bz; #(tck/2-tih); CK_PAD=0; CKN_PAD=1; #(tck/2-tis); end endtask task preactive; input [8:0] sect; input [1:0] bank; begin CKE_PAD=1; BA_PAD=bank; APAD=\{4'h0,sect\}; CEN_PAD=0; WEN_PAD=0; RASN_PAD=0; CASN_PAD=1; #tis; CK_PAD=1; CKN_PAD=0; #tih; APAD='bz; BA_PAD='bz; CEN_PAD=1'bz; WEN_PAD=1'bz; RASN_PAD=1'bz; CASN_PAD=1'bz; #(tck/2-tih); CK_PAD=0; CKN_PAD=1; #(tck/2-tis); end endtask task active; input [25:0] add; input [1:0] bank; begin CKE_PAD=1; BA_PAD=bank; APAD=add[16:4]; CEN_PAD=0; WEN_PAD=1; RASN_PAD=0; CASN_PAD=1; #tis; CK_PAD=1; CKN_PAD=0; #tih; APAD='bz; BA_PAD='bz; CEN_PAD=1'bz; WEN_PAD=1'bz; RASN_PAD=1'bz; CASN_PAD=1'bz; #(tck/2-tih); CK_PAD=0; CKN_PAD=1; #(tck/2-tis); end endtask task address; input [25:0] add; input [1:0] bank; begin CKE_PAD=1; BA_PAD=bank; APAD=\{4'h0,add[25:17]\}; CEN_PAD=0; WEN_PAD=0; RASN_PAD=0; CASN_PAD=1; #tis; CK_PAD=1; CKN_PAD=0; #tih; APAD='bz; BA_PAD='bz; CEN_PAD=1'bz; WEN_PAD=1'bz; RASN_PAD=1'bz; CASN_PAD=1'bz; #(tck/2-tih); CK_PAD=0; CKN_PAD=1; #(tck/2-tis); CKE_PAD=1; BA_PAD=bank; APAD=add[16:4]; CEN_PAD=0; WEN_PAD=1; RASN_PAD=0; CASN_PAD=1; #tis; CK_PAD=1; CKN_PAD=0; #tih; APAD='bz; BA_PAD='bz; CEN_PAD=1'bz; WEN_PAD=1'bz; RASN_PAD=1'bz; CASN_PAD=1'bz; #(tck/2-tih); CK_PAD=0; CKN_PAD=1; #(tck/2-tis); end endtask task write; input [12:0] add; input [1:0] bank; input preamble; input postamble; begin wpst = postamble; wpre = preamble; CKE_PAD=1; BA_PAD=bank; APAD=add; CEN_PAD=0; WEN_PAD=0; RASN_PAD=1; CASN_PAD=0; #tis; if(preamble) write_bus_cycles<= #(tdqss-twpre) 1; else write_bus_cycles<= #(tdqss-tds) 1; CK_PAD=1; CKN_PAD=0; #tih; APAD='bz; BA_PAD='bz; CEN_PAD=1'bz; WEN_PAD=1'bz; RASN_PAD=1'bz; CASN_PAD=1'bz; #(tck/2-tih); CK_PAD=0; CKN_PAD=1; #(tck/2-tis); end endtask always @(posedge write_bus_cycles) begin tmp_ndata = ndata; tmp_wpst = wpst; $display("write_bus_cycles:ndata=%d", tmp_ndata); iDQS_PAD =0; if(wpre) begin #(twpre-tds); end for(i=0;i