v {xschem version=2.9.5_RC5 file_version=1.1}
G {type=package
spice_ignore=true
verilog_ignore=true
tedax_ignore=true
template="

-- THIS IS A TEMPLATE, REPLACE WITH ACTUAL CODE OR REMOVE INSTANCE!!
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;
 
    package aaa is
      type real_vector is array(natural range <>) of real;
      constant dx : real := 0.001 ;
 
    procedure assegna(
        signal A      : inout real;
        signal A_OLD  : in real;
               A_VAL  : in real
    );
 
    end aaa; -- end package declaration
 
 
    package body aaa is
 
 
    procedure assegna(
        signal A      : inout real;
        signal A_OLD  : in real;
               A_VAL  : in real ) is
    constant tdelay: time := 0.01 ns;
    begin
     if (A /=  A_VAL) then
        A <= A_OLD+dx, A_VAL after tdelay;
     end if;
    end assegna;
 
 
    end aaa; -- end package body
"}
V {}
S {}
E {}
L 4 0 -10 355 -10 {}
T {PACKAGE} 5 -25 0 0 0.3 0.3 {}
T {HIDDEN} 135 -5 0 0 0.3 0.3 {}