v {xschem version=3.0.0 file_version=1.2}
K {type=7430
template="device=7430 name=U? footprint=DIP14 description=\\"NAND gate with 8 inputs\\" numslots=0 documentation=http://www.semiconductors.philips.com/acrobat/datasheets/74HC_HCT30_CNV_2.pdf GND=GND
Vcc=Vcc
"
tedax_format="footprint @name @footprint
value @name @value
device @name @device
@comptag"
format="@name @pinlist @value @GND @Vcc"

extra="GND Vcc"
extra_pinnumber="7 14"
}
G {}
V {}
S {}
E {}
T {7430} 40 -120 2 1 0.266667 0.266667 {}
T {@name} 40 -210 2 1 0.333333 0.333333 {}


L 4 30 -200 30 -140 {}
L 4 30 -200 70 -200 {}
L 4 30 -140 70 -140 {}
L 4 30 -140 30 0 {}
L 4 30 -300 30 -200 {}

A 4 105 -170 5 0 360 {}

A 4 70 -170 30 270 180 {}




L 3 0 -290 30 -290 {}
B 5 -2.5 -292.5 2.5 -287.5 {pinnumber=1
pinseq=1
name=A
dir=in
}
T {@#0:pinnumber} 20 -295 2 0 0.266667 0.266667 {layer=13}
L 3 0 -250 30 -250 {}
B 5 -2.5 -252.5 2.5 -247.5 {pinnumber=2
pinseq=2
name=B
dir=in
}
T {@#1:pinnumber} 20 -255 2 0 0.266667 0.266667 {layer=13}
L 3 0 -210 30 -210 {}
B 5 -2.5 -212.5 2.5 -207.5 {pinnumber=3
pinseq=3
name=C
dir=in
}
T {@#2:pinnumber} 20 -215 2 0 0.266667 0.266667 {layer=13}
L 3 0 -170 30 -170 {}
B 5 -2.5 -172.5 2.5 -167.5 {pinnumber=4
pinseq=4
name=D
dir=in
}
T {@#3:pinnumber} 20 -175 2 0 0.266667 0.266667 {layer=13}
L 3 0 -130 30 -130 {}
B 5 -2.5 -132.5 2.5 -127.5 {pinnumber=5
pinseq=5
name=E
dir=in
}
T {@#4:pinnumber} 20 -135 2 0 0.266667 0.266667 {layer=13}
L 3 0 -90 30 -90 {}
B 5 -2.5 -92.5 2.5 -87.5 {pinnumber=6
pinseq=6
name=F
dir=in
}
T {@#5:pinnumber} 20 -95 2 0 0.266667 0.266667 {layer=13}
L 3 0 -50 30 -50 {}
B 5 -2.5 -52.5 2.5 -47.5 {pinnumber=11
pinseq=7
name=G
dir=in
}
T {@#6:pinnumber} 20 -55 2 0 0.266667 0.266667 {layer=13}
L 3 0 -10 30 -10 {}
B 5 -2.5 -12.5 2.5 -7.5 {pinnumber=12
pinseq=8
name=H
dir=in
}
T {@#7:pinnumber} 20 -15 2 0 0.266667 0.266667 {layer=13}
L 3 110 -170 130 -170 {}
B 5 127.5 -172.5 132.5 -167.5 {pinnumber=8
pinseq=9
name=Y
dir=out
}
T {@#8:pinnumber} 110 -175 2 1 0.266667 0.266667 {layer=13}