v {xschem version=3.0.0 file_version=1.2}
K {type=4082
template="name=U? numslots=2 slot=1 device=4082 footprint=DIP14 description=\\"2 AND gates with 4 inputs\\" documentation=http://www.semiconductors.philips.com/acrobat/datasheets/HEF4082B_CNV_3.pdf VDD=VDD
VSS=VSS
"
tedax_format="footprint @name @footprint
value @name @value
device @name @device
@comptag"
format="@name @pinlist @value @VDD @VSS"

extra="VDD VSS"
extra_pinnumber="14 7"
}
G {}
V {}
S {}
E {}
T {@name} 40 -110 2 1 0.333333 0.333333 {}
T {4082} 40 -20 2 1 0.333333 0.333333 {}


L 4 30 -140 30 0 {}
L 4 30 -100 70 -100 {}
L 4 30 -40 70 -40 {}


A 4 70 -70 30 270 180 {}




L 3 0 -130 30 -130 {}
B 5 -2.5 -132.5 2.5 -127.5 {
pinseq=1
dir=in
name=A
pinnumber=2:9
}
T {@#0:pinnumber} 20 -135 2 0 0.266667 0.266667 {layer=13}
L 3 0 -90 30 -90 {}
B 5 -2.5 -92.5 2.5 -87.5 {
pinseq=2
dir=in
name=B
pinnumber=3:10
}
T {@#1:pinnumber} 20 -95 2 0 0.266667 0.266667 {layer=13}
L 3 0 -50 30 -50 {}
B 5 -2.5 -52.5 2.5 -47.5 {
pinseq=3
dir=in
name=C
pinnumber=4:11
}
T {@#2:pinnumber} 20 -55 2 0 0.266667 0.266667 {layer=13}
L 3 0 -10 30 -10 {}
B 5 -2.5 -12.5 2.5 -7.5 {
pinseq=4
dir=in
name=D
pinnumber=5:12
}
T {@#3:pinnumber} 20 -15 2 0 0.266667 0.266667 {layer=13}
L 3 100 -70 130 -70 {}
B 5 127.5 -72.5 132.5 -67.5 {
pinseq=5
dir=out
name=Y
pinnumber=1:13
}
T {@#4:pinnumber} 110 -75 2 1 0.266667 0.266667 {layer=13}