v {xschem version=3.0.0 file_version=1.2}
K {type=4082
template="name=U? numslots=2 slot=1 device=4082 footprint=DIP14 description=\\"2 AND gates with 4 inputs\\" documentation=http://www.semiconductors.philips.com/acrobat/datasheets/HEF4082B_CNV_3.pdf symversion=1.0 VDD=VDD
VSS=VSS
"
tedax_format="footprint @name @footprint
value @name @value
device @name @device
@comptag"
format="@name @pinlist @value @VDD @VSS"

extra="VDD VSS"
extra_pinnumber="14 7"
}
G {}
V {}
S {}
E {}
T {@name} 40 -100 2 1 0.333333 0.333333 {}
T {4082} 40 -10 2 1 0.266667 0.266667 {}


L 4 30 -90 30 -30 {}
L 4 30 -90 70 -90 {}
L 4 30 -30 70 -30 {}
L 4 30 -30 30 -10 {}
L 4 30 -110 30 -90 {}
L 4 30 -120 30 -110 {}
L 4 30 -10 30 0 {}


A 4 70 -60 30 270 180 {}




L 3 0 -110 30 -110 {}
B 5 -2.5 -112.5 2.5 -107.5 {
pinseq=1
dir=in
name=A
pinnumber=2:9
}
T {@#0:pinnumber} 20 -115 2 0 0.266667 0.266667 {layer=13}
L 3 0 -80 30 -80 {}
B 5 -2.5 -82.5 2.5 -77.5 {
pinseq=2
dir=in
name=B
pinnumber=3:10
}
T {@#1:pinnumber} 20 -85 2 0 0.266667 0.266667 {layer=13}
L 3 0 -40 30 -40 {}
B 5 -2.5 -42.5 2.5 -37.5 {
pinseq=3
dir=in
name=C
pinnumber=4:11
}
T {@#2:pinnumber} 20 -45 2 0 0.266667 0.266667 {layer=13}
L 3 0 -10 30 -10 {}
B 5 -2.5 -12.5 2.5 -7.5 {
pinseq=4
dir=in
name=D
pinnumber=5:12
}
T {@#3:pinnumber} 20 -15 2 0 0.266667 0.266667 {layer=13}
L 3 100 -60 130 -60 {}
B 5 127.5 -62.5 132.5 -57.5 {
pinseq=5
dir=out
name=Y
pinnumber=1:13
}
T {@#4:pinnumber} 110 -65 2 1 0.266667 0.266667 {layer=13}