v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=probe
format=".save v(@@p\\\\) v(@@m\\\\)"
template="name=p1"}
V {}
S {}
E {}
L 15 0 -15 0 -10 {}
L 15 -2.5 -12.5 2.5 -12.5 {}
L 15 -2.5 12.5 2.5 12.5 {}
B 5 -1.25 -21.25 1.25 -18.75 {name=p dir=in}
B 5 -1.25 18.75 1.25 21.25 {name=m dir=in}
T {@spice_get_diff_voltage} 1.875 -6.09375 0 0 0.2 0.2 {layer=15 hcenter=true}