v {xschem version=3.4.5 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=short
template="name=x1 value=0.1"
format="* short @name : @#0:net_name <--> @#1:net_name"
highlight=true}
V {}
S {}
E {}
L 1 0 -30 0 30 {}
B 5 -2.5 -32.5 2.5 -27.5 {name=A dir=inout }
B 5 -2.5 27.5 2.5 32.5 {name=A dir=inout }
T {short} 22.5 -26 0 0 0.3 0.3 { layer=3
hcenter=true}
T {@name} 5 8 0 0 0.2 0.2 {}