v {xschem version=3.4.6 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=pnp
format="@spiceprefix@name @pinlist @model area=@area m=@m"

tedax_format="footprint @name @footprint
value @name @value
device @name @device
spicedev @name @spicedev
spiceval @name @spiceval
comptag @name @comptag"

template="name=Q1
model=Q2N2907
device=2N2907
footprint=TO92
area=1
m=1"}
V {}
S {}
E {}
L 4 0 -30 0 30 {}
L 4 -20 0 0 0 {}
L 4 10 -20 20 -30 {}
L 4 0 10 20 30 {}
B 5 17.5 27.5 22.5 32.5 {name=C dir=inout pinnumber=3}
B 5 -22.5 -2.5 -17.5 2.5 {name=B dir=in pinnumber=1}
B 5 17.5 -32.5 22.5 -27.5 {name=E dir=inout pinnumber=2}
P 4 4 0 -10 15 -15 5 -25 0 -10 {fill=true}
T {@model} 20 -12.5 0 0 0.2 0.2 {}
T {@name} 20 0 0 0 0.2 0.2 {}
T {@#2:pinnumber} 25 -25 0 0 0.2 0.2 {layer=13}
T {@#0:pinnumber} 25 12.5 0 0 0.2 0.2 {layer=13}
T {@#1:pinnumber} -5 6.25 0 1 0.2 0.2 {layer=13}
T {@#2:net_name} 25 -33.75 0 0 0.15 0.15 {layer=15 hide=instance}
T {@#0:net_name} 25 23.75 0 0 0.15 0.15 {layer=15 hide=instance}
T {@#1:net_name} -6.25 -12.5 0 1 0.15 0.15 {layer=15 hide=instance}
T {@spice_get_current} 40 11.25 0 0 0.2 0.2 {layer=17}