v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=noconn
format="* noconn @#0:net_name"
vhdl_format="-- noconn @#0:net_name"
verilog_format="// noconn @#0:net_name"
tedax_format="# noconn @#0:net_name"
template="name=l1"}
V {}
S {}
E {}
L 4 -3.75 0 0 -0 {}
B 5 -1.25 -1.25 1.25 1.25 {name=p dir=inout}
T {@#0:net_name} -20.625 -4.375 0 1 0.15 0.15 {layer=15 hide=instance}
T {NC} -16.25 -4.375 0 0 0.15 0.15 { layer=4}