v {xschem version=3.4.6 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=resistor
format="@name @pinlist 0.01 m=@m"
template="name=R1 m=1"}
V {}
S {}
E {}
L 4 2.5 -22.5 7.5 -22.5 {}
L 4 5 -25 5 -20 {}
L 4 0 -30 -0 -15 {}
L 4 0 -15 5 -15 {}
L 4 5 -15 5 15 {}
L 4 -5 15 5 15 {}
L 4 -5 -15 -5 15 {}
L 4 -5 -15 0 -15 {}
L 4 -0 15 -0 30 {}
L 4 -5 -10 -0 -15 {}
L 4 -5 -5 5 -15 {}
L 4 -5 -0 5 -10 {}
L 4 -5 5 5 -5 {}
L 4 -5 10 5 0 {}
L 4 -5 15 5 5 {}
L 4 0 15 5 10 {}
B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=out propag=1}
B 5 -2.5 27.5 2.5 32.5 {name=m dir=in propag=0}
T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15 hide=instance}
T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15 hide=instance}