v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
}

T {@symname} -13.5 -6 0 0 0.3 0.3 {}
T {@name} 135 -42 0 0 0.2 0.2 {}
L 4 -130 -30 130 -30 {}
L 4 -130 30 130 30 {}
L 4 -130 -30 -130 30 {}
L 4 130 -30 130 30 {}
B 5 147.5 -22.5 152.5 -17.5 {name=bcd2[1:0] verilog_type=reg dir=out }
L 4 130 -20 150 -20 {}
T {bcd2[1:0]} 125 -24 0 1 0.2 0.2 {}
B 5 -152.5 -22.5 -147.5 -17.5 {name=ibin[7:0] dir=in }
L 4 -150 -20 -130 -20 {}
T {ibin[7:0]} -125 -24 0 0 0.2 0.2 {}
B 5 147.5 -2.5 152.5 2.5 {name=bcd1[3:0] verilog_type=reg dir=out }
L 4 130 0 150 0 {}
T {bcd1[3:0]} 125 -4 0 1 0.2 0.2 {}
B 5 147.5 17.5 152.5 22.5 {name=bcd0[3:0] verilog_type=reg dir=out }
L 4 130 20 150 20 {}
T {bcd0[3:0]} 125 16 0 1 0.2 0.2 {}