v {xschem version=2.9.5_RC5 file_version=1.1}
G {type=gate
verilog_format = "assign #@del @@Y = ~( @@A[max:0] | @@B[max:0] );"
vhdl_format="@@Y <= @@A[max:0] nor @@B[max:0] after @del ps ;"
format="@name [ @@A[max:0] @@B[max:0] ] @@Y nor"
template="name=a1 del=200"}
V {}
S {}
E {}
L 4 45 0 60 0 {}
L 4 -40 -20 -19.21875 -20 {}
L 4 -40 20 -19.21875 20 {}
L 4 -25 -30 -5 -30 {}
L 4 -25 30 -5 30 {}
B 5 57.5 -2.5 62.5 2.5 {name=Y dir=out verilog_type=wire}
B 5 -42.5 -22.5 -37.5 -17.5 {name=A[max:0] dir=in}
B 5 -42.5 17.5 -37.5 22.5 {name=B[max:0] dir=in}
A 4 40 0 5 180 360 {}
A 4 -65 0 50 323.130102354156 73.7397952916881 {}
A 4 -9.642857142857142 17.85714285714286 48.0818286351295 21.80140948635181 62.65738573560834 {}
A 4 -4.6875 -11.25 41.25118369513777 269.5659493678606 74.60789655596687 {}
T {@name} -11.25 1.25 0 0 0.2 0.2 {}
T {NR2} -12.8125 -18.75 0 0 0.3 0.3 {}