v {xschem version=2.9.5 file_version=1.1}
G {type=gate
verilog_format="assign #@del @@Y = ~( @@A[max:0] & @@B[max:0] );"
vhdl_format = "@@Y <= @@A[max:0] nand @@B[max:0] after @del ps;"
format="@name [ @@A[max:0] @@B[max:0] ] @@Y nand"
template="name=a1 del=120"}
V {}
S {}
E {}
L 4 -40 -20 -25 -20 {}
L 4 -25 -30 -25 30 {}
L 4 -40 20 -25 20 {}
L 4 -25 -30 10 -30 {}
L 4 -25 30 10 30 {}
L 4 50 0 60 -0 {}
B 5 57.5 -2.5 62.5 2.5 {name=Y dir=out verilog_type=wire}
B 5 -42.5 -22.5 -37.5 -17.5 {name=A[max:0] dir=in}
B 5 -42.5 17.5 -37.5 22.5 {name=B[max:0] dir=in}
A 4 10 0 30 270 180 {}
A 4 45 -0 5 180 360 {}
T {ND2} -17.5 -25 0 0 0.3 0.3 {}
T {@name} -21.25 -5 0 0 0.2 0.2 {}