v {xschem version=2.9.5_RC5 file_version=1.1}
G {type=subcircuit
vhdl_stop=true
verilog_stop=true
format="@name @pinlist @symname"
template="name=x1 delay=\\"220 ps\\" del=220 "
generic_type="delay=time"}
V {}
S {}
E {}
L 4 -40 -20 -27.5 -20 {}
L 4 35 0 60 0 {}
L 4 -40 20 -27.5 20 {}
L 4 -25 -30 -5 -30 {}
L 4 -25 30 -5 30 {}
B 5 57.5 -2.5 62.5 2.5 {name=Y verilog_type=wire dir=out}
B 5 -42.5 -22.5 -37.5 -17.5 {name=A dir=in}
B 5 -42.5 17.5 -37.5 22.5 {name=B dir=in}
A 4 -9.642857142857142 17.85714285714286 48.0818286351295 21.80140948635181 62.65738573560834 {}
A 4 -4.6875 -11.25 41.25118369513777 269.5659493678606 74.60789655596687 {}
A 4 -65 0 50 323.130102354156 73.7397952916881 {}
A 4 -72.5 0 50 323.130102354156 73.7397952916881 {}
T {@name} -8.75 -5 0 0 0.2 0.2 {}
T {EO} -10 -25 0 0 0.3 0.3 {}