v {xschem version=2.9.5_RC5 file_version=1.1}
G {type=port_attributes
spice_ignore=true
verilog_ignore=true
tedax_ignore=true
template="
 attribute async_set_reset of RPTL : signal is "true";
"}
V {}
S {}
E {}
L 4 -0 -10 355 -10 {}
T {VHDL PORT ATTRIBUTES} 5 -25 0 0 0.3 0.3 {}
T {@prop_ptr} 45 5 0 0 0.2 0.2 {}