v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {type=subcircuit
format="@name @pinlist @VCCPIN @VSSPIN @symname WN=@WN LN=@LN WP=@WP LP=@LP"
template="name=x1 WN=2u LN=1.2u WP=2u LP=1.2u VCCPIN=VCC VSSPIN=VSS"
extra="VCCPIN VSSPIN"
generic_type="VCCPIN=string VSSPIN=string"}
V {}
S {}
E {}
L 4 -5 -18.75 -5 -13.75 {}
L 4 -5 -18.75 -2.5 -21.25 {}
L 4 -2.5 -21.25 2.5 -21.25 {}
L 4 2.5 -21.25 5 -18.75 {}
L 4 5 -18.75 5 -13.75 {}
L 4 2.5 -11.25 5 -13.75 {}
L 4 -5 -13.75 -2.5 -11.25 {}
L 4 -20 -20 -20 0 {}
L 4 -20 0 20 -20 {}
L 4 20 -20 20 0 {}
L 4 -20 -20 20 0 {}
L 4 0 -30 0 -21.25 {}
L 4 -20 0 -20 20 {}
L 4 -20 20 20 0 {}
L 4 20 0 20 20 {}
L 4 -20 0 20 20 {}
L 4 0 10 0 30 {}
L 4 -40 0 -20 0 {}
L 4 20 0 40 0 {}
B 5 37.5 -2.5 42.5 2.5 {name=Z dir=inout}
B 5 -42.5 -2.5 -37.5 2.5 {name=A dir=inout}
B 5 -2.5 -32.5 2.5 -27.5 {name=EN dir=in}
B 5 -2.5 27.5 2.5 32.5 {name=E dir=in}
T {@name} 8.75 -35 0 0 0.2 0.2 {}
T {@WP} -20 -30 0 1 0.2 0.2 {}
T {@WN} -20 20 0 1 0.2 0.2 {}