v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 -60 -50 60 -50 {}
L 4 -60 50 60 50 {}
L 4 -60 -50 -60 50 {}
L 4 60 -50 60 50 {}
L 4 -80 -40 -60 -40 {}
L 4 -80 20 -60 20 {}
L 4 -80 40 -60 40 {}
L 4 60 -40 80 -40 {}
L 4 -30 50 -30 70 {}
L 4 -10 50 -10 70 {}
L 4 10 50 10 70 {}
L 4 30 50 30 70 {}
B 5 -82.5 -42.5 -77.5 -37.5 {name=D dir=in }
B 5 -82.5 17.5 -77.5 22.5 {name=G dir=in }
B 5 -82.5 37.5 -77.5 42.5 {name=CD dir=in }
B 5 77.5 -42.5 82.5 -37.5 {name=Q dir=out }
B 5 -32.5 67.5 -27.5 72.5 {name=vcc dir=inout }
B 5 -12.5 67.5 -7.5 72.5 {name=vss dir=inout }
B 5 7.5 67.5 12.5 72.5 {name=vccsup dir=inout }
B 5 27.5 67.5 32.5 72.5 {name=vsssup dir=inout }
T {@symname} -54 -6 0 0 0.3 0.3 {}
T {@name} 65 -62 0 0 0.2 0.2 {}
T {D} -55 -44 0 0 0.2 0.2 {}
T {G} -55 16 0 0 0.2 0.2 {}
T {CD} -55 36 0 0 0.2 0.2 {}
T {Q} 55 -44 0 1 0.2 0.2 {}