v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=opamp
format="@spiceprefix@name @#0 @#1 @VCC @VNN @#2 @model"

tedax_format="footprint @name @footprint
value @name @value
device @name @device
spicedev @name @spicedev
spiceval @name @spiceval
comptag @name @comptag"

template="name=U1:1 
model=LM358 device=LM358 
footprint=so(8) 
numslots=2 
VCC=VCC 
VNN=VNN"

extra="VCC VNN"
extra_pinnumber="8 4"}
V {}
S {}
E {}
L 4 110 0 130 0 {}
L 4 -80 -40 -60 -40 {}
L 4 -80 40 -60 40 {}
L 4 -60 -70 110 0 {}
L 4 -60 70 110 0 {}
L 4 -60 -70 -60 70 {}
B 5 -82.5 -42.5 -77.5 -37.5 {name=PLUS sig_type=std_logic dir=in pinnumber=3:5}
B 5 -82.5 37.5 -77.5 42.5 {name=MINUS sig_type=std_logic dir=in pinnumber=2:6}
B 5 127.5 -2.5 132.5 2.5 {name=OUT sig_type=std_logic dir=out pinnumber=1:7}
T {@device} -48.5 -11 0 0 0.3 0.3 {}
T {@name} 0 -62 0 0 0.3 0.3 {}
T {@#2:pinnumber} 115 -14 0 0 0.2 0.2 {layer=13}
T {@#0:pinnumber} -65 -54 0 1 0.2 0.2 {layer=13}
T {@#1:pinnumber} -65 26 0 1 0.2 0.2 {layer=13}
T {OUT} 90 -4 0 1 0.2 0.2 {}
T {PLUS} -55 -44 0 0 0.2 0.2 {}
T {MINUS} -55 36 0 0 0.2 0.2 {}