v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 -40 -30 40 -30 {}
L 4 -40 30 40 30 {}
L 4 -40 -30 -40 30 {}
L 4 40 -30 40 30 {}
L 4 -60 -20 -40 -20 {}
L 4 -60 0 -40 0 {}
L 4 40 -20 60 -20 {}
L 4 -60 20 -40 20 {}
B 5 -62.5 -22.5 -57.5 -17.5 {name=D dir=in }
B 5 -62.5 -2.5 -57.5 2.5 {name=CLK dir=in }
B 5 57.5 -22.5 62.5 -17.5 {name=Q dir=out }
B 5 -62.5 17.5 -57.5 22.5 {name=RST dir=in }
T {@symname} -64.5 34 0 0 0.3 0.3 {}
T {@name} 45 -42 0 0 0.2 0.2 {}
T {D} -35 -24 0 0 0.2 0.2 {}
T {CLK} -35 -4 0 0 0.2 0.2 {}
T {Q} 35 -24 0 1 0.2 0.2 {}
T {RST} -35 16 0 0 0.2 0.2 {}