v {xschem version=3.4.4 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. * Copyright (C) 1998-2023 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA } K {type=symbol template="graphical=1 " tedax_format="footprint @name @footprint value @name @value device @name @device @comptag" format="@name @pinlist @value " } G {} V {} S {} E {} T {FILE:} 950 -40 2 1 0.266667 0.266667 {} T {REVISION:} 1300 -40 2 1 0.266667 0.266667 {} T {DRAWN BY: } 1300 -10 2 1 0.266667 0.266667 {} T {PAGE} 950 -10 2 1 0.266667 0.266667 {} T {OF} 1120 -10 2 1 0.266667 0.266667 {} T {TITLE} 950 -70 2 1 0.266667 0.266667 {} L 4 0 0 1700 0 {} L 4 1700 -1100 1700 0 {} L 4 0 -1100 1700 -1100 {} L 4 0 -1100 0 0 {} L 4 940 0 1700 0 {} L 4 1700 -140 1700 0 {} L 4 940 -140 1700 -140 {} L 4 940 -140 940 0 {} L 4 1290 -60 1290 0 {} L 4 940 -60 1700 -60 {}