v {xschem version=3.4.4 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. * Copyright (C) 1998-2023 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA } G {} K {type=logo template="name=l1 author=\\"Stefan Schippers\\" rev=1.0 lock=false" verilog_ignore=true vhdl_ignore=true spice_ignore=true tedax_ignore=true } V {} S {} E {} L 4 385 0 2500 0 {} L 4 0 0 65 0 {} L 4 2500 -1770 2500 0 {} L 4 0 -1770 2500 -1770 {} L 4 0 -1770 0 0 {} L 4 1180 -160 1180 0 {} L 4 1180 -160 2500 -160 {} L 4 1180 -80 2500 -80 {} L 4 1810 -80 1810 0 {} L 4 1810 -160 1810 -80 {} L 4 1520 -80 1520 0 {} P 5 13 165 -30 135 0 165 30 145 30 125 10 105 30 85 30 115 0 85 -30 105 -30 125 -10 145 -30 165 -30 {fill=true} T {SCHEM} 165 -25 0 0 1 1 {} T {@time_last_modified} 1820 -60 0 0 0.8 0.8 {} T {@author} 1190 -140 0 0 0.8 0.8 {} T {Page @page of @pages} 1190 -60 0 0 0.8 0.8 {} T {@title} 1820 -120 0 0 0.6 0.6 {vcenter=true} T {Rev. @rev} 1530 -60 0 0 0.8 0.8 {}