v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {type=subcircuit
format="@name @pinlist @symname"
template="name=x1 cap=10.0"
generic_type="cap=real"
}
V {}
S {}
E {}
L 4 0 5 0 30 {}
L 4 0 -30 0 -5 {}
L 4 -10 -5 10 -5 {}
L 4 -10 5 10 5 {}
L 4 2.5 -22.5 7.5 -22.5 {}
L 4 5 -25 5 -20 {}
L 4 -5 30 5 30 {}
L 4 0 35 5 30 {}
L 4 -5 30 0 35 {}
B 5 -2.5 -32.5 2.5 -27.5 {name=USC sig_type=rreal verilog_type=wire dir=inout }
T {@symname} 14.5 -6 0 0 0.3 0.3 {}
T {@name} 15 -17 0 0 0.2 0.2 {}
T {USC} -5 -24 0 1 0.2 0.2 {}
T {@cap pF} 14.5 14 0 0 0.3 0.3 {}