stefan schippers
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94bccc08d9
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do not duplicate empty strings as NULLs in hash tables
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2023-10-09 12:49:11 +02:00 |
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stefan schippers
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832e89ce1b
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update test_ngspice.sch example circuit
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2023-03-09 20:44:51 +01:00 |
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Stefan Frederik
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bc33261f90
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better parsing xxx='<expr>' or xxx={expr} patterns in flatten.awk. Doc upcates, test circuit updates.
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2022-10-20 20:25:49 +02:00 |
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Stefan Frederik
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aa6b8f0123
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Doc updates (sim_pinnumber), example circuits update
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2022-10-17 12:45:48 +02:00 |
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Stefan Frederik
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fc576f69ac
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sort symbol pins if key pinnumber is present on all of them
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2022-10-16 16:18:38 +02:00 |
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Stefan Frederik
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3f627123b2
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persists highlights on instances: remove highlighted instance from hash if user selects and presses ctrl-k as it is done for nets. Avoid instance highlight to also highlight net with identical name (example instance x1 and net x1). Verilog and Vhdl netlists handle duplicated (pass-through) pins
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2022-10-11 13:12:17 +02:00 |
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Stefan Frederik
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f0e21f15bd
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revert testbench.sch changes
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2022-06-14 10:27:30 +02:00 |
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Stefan Frederik
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be43fe41b0
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added bit blasting option (default: disabled) in menu for verilog netlists: group bit slices in instance net assignments. Doc updates (FSiC-2022)
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2022-06-14 10:20:06 +02:00 |
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Stefan Frederik
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4cb0eb0491
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better check for availability of -justify option in listboxes
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2022-05-29 00:36:19 +02:00 |
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Stefan Frederik
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ba15e21b24
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preserve ordering in verilog/VHDL signal/wire/reg declarations for consistent netlist hashing/checking
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2021-12-15 15:17:45 +01:00 |
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Stefan Frederik
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f94d3b5c15
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removed comment in schematic test_verilog_verilog.sch
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2021-12-01 15:58:26 +01:00 |
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Stefan Frederik
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756a7ba06d
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swap s/d in verilog netlisting rule for enhancement load "rnmos4.sym" so it can be used as usually done with nmos devices (drain side up) .
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2021-12-01 15:53:14 +01:00 |
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Stefan Frederik
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dcb37ef295
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added devices/rnmos4.sym for enhancement load nmos gate simulation in verilog, updated test_mos_verilog.sch example
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2021-12-01 14:25:27 +01:00 |
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Stefan Frederik
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9bca5b3f5b
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fix descend_symbol regression due to previous commit
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2021-11-22 00:42:53 +01:00 |
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Stefan Frederik
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7f9ee9fc2a
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add "xschem check_symbols" and "xschem reload_symbols" for future checking of symbols that are newer wrt to schematic. set mtime of newly created schematic (that does not exist on disk) to current time. Add verilog attributes to devices/pmos4.sym
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2021-11-21 12:28:36 +01:00 |
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Stefan Frederik
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95095e97d0
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add delays in logic/test_mos_verilog.sch
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2021-11-21 01:45:16 +01:00 |
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Stefan Frederik
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0e91351e4a
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fix depletion mos example
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2021-11-21 01:18:12 +01:00 |
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Stefan Frederik
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94934b8989
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added test_mos_verilog.sym example in top schematic page
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2021-11-21 00:53:37 +01:00 |
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Stefan Frederik
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64586f0c2d
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depletion nmos transistor drawn with drain side low as this is the way it is used
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2021-11-21 00:02:48 +01:00 |
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Stefan Frederik
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10114ec838
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add missing braces in update recent file submenu, fix file selector improperly setting main window title, added logic/test_mos_verilog.sch depletion mode verilog example
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2021-11-20 23:44:19 +01:00 |
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Stefan Frederik
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b7b9d666a9
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fix: avoid doing any erc checking/highlights if a schematic is explicitly loaded without linking components to symbols. This is done for instances with (spice|verilog)_stop=true attributes set to prevent unwanted symbol expansion
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2020-12-23 18:16:53 +01:00 |
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Stefan Schippers
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f8f1626c1b
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cleanup in print_spice_element(), print_verilog_primitive(), print_vhdl_primitive(), print_tedax_element(), parselabel allows ~ in node names (XSPICE inversion operator)
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2020-10-13 02:52:37 +02:00 |
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Stefan SChippers
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5e8df730a0
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |