stefan schippers
|
f8f7c4f230
|
updated moude_bindings.tcl with Paul`s new version, updated noconn.sym (do not use *_ignore attributes, put comments in netlist about NC net)
|
2023-06-30 09:11:04 +02:00 |
|
stefan schippers
|
245993f034
|
added attributes spice_ignore=short, verilog_ignore=short, .... that will transform the instance into a short in the current netlisting mode, shorting all pins to the same net. Works similarly as lvs_ignore=short, but does not need lvs_ignore global setting
|
2023-06-07 03:41:49 +02:00 |
|
stefan schippers
|
394db224d1
|
added global tcl variable `lvs_ignore` that can be used to enable instance or symbol attributes `lvs_ignore=open` or `lvs_ignore=short` while netlisting, added `test_lvs_ignore.sch` example
|
2023-06-06 15:22:45 +02:00 |
|
stefan schippers
|
ff216e8187
|
function reset_flags() set flags on symbols and instances; call reset_flags before rebuilding connectivity to update cached values; add short.sym component that can be used to short two nets together (and remove the short using *_ignore=true); instcheck(): do not proces instances that have *_ignore=true set.
|
2023-06-06 08:42:43 +02:00 |
|
stefan schippers
|
4f387f3bbe
|
disable displaying backannotation data if `b` cursor is hidden or `Simulation->Live annotation with b cursor` is disabled. Use resolved_net() in translate() when displaying @spice_get_voltage so it will work on sub block ports
|
2023-06-05 12:58:19 +02:00 |
|
stefan schippers
|
5085301cd7
|
add net_name=true in bus_tap.sym (so avoid setting it on instancs), add documentation for bus taps
|
2023-05-30 11:03:07 +02:00 |
|
stefan schippers
|
5043b14921
|
fix uninitialized wave_color due to regression after rainbow wave color enablement in double dc sweeps; more bus_tap.sym usage in examples; make bus_tap.sym work correctly for all netlist formats
|
2023-05-27 23:36:10 +02:00 |
|
stefan schippers
|
cf61c253c5
|
fix a bug in my_mstrcat if an empty string is appended; add resolved_net(n) function that returns the top-most hierarchy name of the net mapping to upper level port connections if any; add xschem resolved_net comand that returns the resolved_net of selected wire/label/pin; add @#n:resolved_net pattern in symbol texts that uses resolved_net
|
2023-05-27 11:20:49 +02:00 |
|
stefan schippers
|
d3b99d3a76
|
update n and p jfets, added pjfet simulation
|
2023-05-24 10:02:26 +02:00 |
|
stefan schippers
|
608a144dd1
|
fix tcl procedures using find_file to find a component: use find_file_first (return 1st match) , since find_file may return multiple matches; add njfet.sym, pjfet.sym and test_jfet.sch
|
2023-05-24 08:43:05 +02:00 |
|
Stefan Schippers
|
1774ff4e3a
|
allow @#n:pin_attr or @#pin_name:pin_attr in spice format string (print_spice_element), in addition to @#n (convergence to translate()
|
2023-05-22 21:50:14 +02:00 |
|
stefan schippers
|
0f1bbd24c8
|
devices/bus_tap.sym: remove format attr in symbol
|
2023-05-22 11:52:51 +02:00 |
|
stefan schippers
|
a4d5ddb63f
|
add examples/test_bus_tap.sch
|
2023-05-22 00:49:54 +02:00 |
|
stefan schippers
|
ea533bd9e3
|
added bus_tap.sym
|
2023-05-21 23:59:50 +02:00 |
|
stefan schippers
|
f110e817ef
|
ammeter.sym type set to "ammeter" instead of "probe", so will be greyed out if *_ignore attr is set
|
2023-05-11 00:47:59 +02:00 |
|
stefan schippers
|
339c523f0b
|
align symbol types, reducing number of different types (remove ngprobe, current_probe, differential_probe, raw_data_show --> probe
|
2023-05-10 17:46:16 +02:00 |
|
stefan schippers
|
0a4f942fb7
|
symbol_ignore=true attribute can be set on all symbol elements (text, lines, rectangles, arcs, polys, instances, nets) such that these marked elements are not displayed when symbol is instantiated.
|
2023-05-09 23:26:46 +02:00 |
|
stefan schippers
|
6b857f7b7d
|
switch_ngspice.sym: show (in very small font) @device_model (if given)
|
2023-04-30 10:37:45 +02:00 |
|
stefan schippers
|
fc18a69109
|
ind.sym artwork
|
2023-04-28 11:23:06 +02:00 |
|
stefan schippers
|
01bc76955e
|
fix simulator_commands_shown.sym (wrong and incompete quoting)
|
2023-02-13 19:15:35 +01:00 |
|
stefan schippers
|
e5227d6a31
|
rename top_subckt to lvs_netlist (more appropriate), better tcp interface (redirect stdout to socket in addition to command return value)
|
2023-02-09 11:30:27 +01:00 |
|
stefan schippers
|
af22c256b3
|
default to unlocked state (lock=false) at title 1st placement
|
2023-01-07 11:34:47 +01:00 |
|
stefan schippers
|
4c0d5023f5
|
allow 0 width lines (faster device dependent implementation) if user defined line width is set (to 0), add devices/title-3.sym
|
2023-01-07 11:28:28 +01:00 |
|
stefan schippers
|
19757ddd8a
|
add menu properties -> Edit header/License text, to allow inserting header or license metadata into the sch/sym file.
|
2023-01-02 03:04:35 +01:00 |
|
stefan schippers
|
609033e7ca
|
fix regression (not allowing to change text size)
|
2022-11-23 16:57:21 +01:00 |
|
Stefan Schippers
|
e7851d01db
|
"xschem set format <fmt_attribute>" will change netlisting format attribute instead of default "format" (or verilog_format or vhdl_format), however fallback to default netlisting rule attribute if not defined in symbol. add tcl function "from_eng <n>" to convert spice formatted numbers to floating point
|
2022-11-23 16:16:38 +01:00 |
|
Stefan Frederik
|
3d49ca63c9
|
avoid tcleval() of strings returned by translate2(), show currents of resistors and diodes when annotating.
|
2022-11-04 13:35:06 +01:00 |
|
Stefan Frederik
|
b98d836be3
|
devices/simulator_commands.sym: avoid recursive @param substitution in spice commands
|
2022-11-03 11:00:15 +01:00 |
|
Stefan Frederik
|
b36cd99e01
|
update simulator_commands.sym (missing close parenthesis at end, not causing any problem though)
|
2022-11-02 23:11:23 +01:00 |
|
Stefan Frederik
|
666b0ebd5b
|
show @path in title.sym
|
2022-11-01 13:26:22 +01:00 |
|
Stefan Frederik
|
b1f011f933
|
clean up testing @path in symbols
|
2022-11-01 13:17:51 +01:00 |
|
Stefan Frederik
|
b0a88325e7
|
"@path" will be expanded in symbols with the hierarchy path, so a fully qualified instance name is obtained with @path@name
|
2022-11-01 12:54:43 +01:00 |
|
Stefan Frederik
|
4c43e77818
|
eliminated hide=true attribute for backannotation current/voltage texts (will be hidden anyway if no sim data is loaded)
|
2022-10-24 17:28:39 +02:00 |
|
Stefan Frederik
|
18044abb3e
|
iopin.sym micro edit
|
2022-10-24 17:06:54 +02:00 |
|
Stefan Frederik
|
b8732f2321
|
ipin,iopin,opin reshaped to better show connection hotspot
|
2022-10-19 10:37:43 +02:00 |
|
Stefan Frederik
|
e14c8b9a11
|
wire labels: default name set to p1 instead of l1, so it will not clash with typical inductor names
|
2022-10-12 16:36:56 +02:00 |
|
Stefan Frederik
|
314acbabda
|
allow tabs and newlines in graph expressions in addition to spaces; updated example schematics
|
2022-09-23 02:18:51 +02:00 |
|
Stefan Frederik
|
3e2bc9f95e
|
added "Annotate operating point" into Simulation menu
|
2022-09-22 19:47:25 +02:00 |
|
Stefan Frederik
|
e61ef2eabf
|
fixed a potential parse error in edit_prop if list_tokens returns a non list due to malformed input. Added @spice_get_diff_voltage to get a voltage difference between 2 nodes.
|
2022-09-22 17:35:14 +02:00 |
|
Stefan Frederik
|
6f907b5430
|
updated test schematics to use new xschem annotate_op instead of ngspice::annotate
|
2022-09-21 18:38:53 +02:00 |
|
Stefan Frederik
|
9c89a08111
|
better backannotation info placement in net labels, fixes in translate() for @spice_get_voltage and @spice_get_current, fixes in ngspice_backannotate routines.
|
2022-09-21 17:24:16 +02:00 |
|
Stefan Frederik
|
931c1520e3
|
make op backannotation in schematic work also if raw file loaded at hierarchy level > 0
|
2022-09-21 13:58:01 +02:00 |
|
Stefan Frederik
|
b542186ebd
|
updated example schematics to new annotate / raw file loading methods
|
2022-09-20 18:25:31 +02:00 |
|
Stefan Frederik
|
8169196b35
|
bypass tcl for voltage and current backannotation in schematic from cursor b positon in graph
|
2022-09-20 03:12:46 +02:00 |
|
Stefan Frederik
|
7abceb3344
|
fix regression in ngspice::get_current, simplified voltage reporting in net label symbols
|
2022-09-20 00:12:27 +02:00 |
|
Stefan Frederik
|
53dc7fe3bf
|
add backannotation info (as hidden text) in lab_pin.sym, lab_wire.sym, transitioning example schematics from old (push) backannotation model to new pull model.
|
2022-09-19 11:22:04 +02:00 |
|
Stefan Frederik
|
3a10b39299
|
fixed current (also hierarchic) reporting in ammeter.sym and vsource.sym)
|
2022-09-19 09:45:35 +02:00 |
|
Stefan Frederik
|
96f80d1d33
|
Alt-a in graph annotates schematic with values at cursor b position. Simulation->Live annotate option to automatically update schematic probes if cursor moved. Some improvements and fixes in ngspice_annotate.tcl. Fix xschem setprobe command. Added missing housekeeping_ctx when a new tab is created. housekeeping_ctx: added more variables to sync.
|
2022-09-18 05:29:16 +02:00 |
|
Stefan Frederik
|
d0b02724cf
|
simpler ngspice_probe.sym
|
2022-09-13 01:33:09 +02:00 |
|
Stefan Frederik
|
907315191d
|
added "devices/simulator_commands*.sym" to conditionally include commands in the netlist depending on selected target simulator
|
2022-09-09 13:06:11 +02:00 |
|
Stefan Frederik
|
5da8f777b2
|
monospaced font in code_shown.sym
|
2022-08-30 15:54:18 +02:00 |
|
Stefan Frederik
|
ce4bd4837a
|
changed @schname to @schname_ext and added @schname that expands to the schematic name containing the instance, with no extension (no .sch)
|
2022-08-10 08:38:49 +02:00 |
|
Stefan Frederik
|
aa63f0adab
|
add devices/res3.sym for generic semiconductor resistance. User must provide a 3-terminal subcircuit for this
|
2022-07-29 09:40:17 +02:00 |
|
Stefan Frederik
|
28cc187b56
|
when placing components with lock=true set in template attribute allow to move it to its final position like any other unlocked symbol. Code in place in verilog.awk to do bit unblasting in net-> port associations, but not enalbed it for now as icarus verilog does not handle some bus slices (for example if bus slice direction is different from declared bus direction)
|
2022-06-09 09:32:34 +02:00 |
|
Stefan Frederik
|
eff273dd08
|
fix in spice.awk: do not clobber user or device format generated .save lines (no ?n tag); add devices/device_param_probe.sym
|
2022-04-30 10:58:15 +02:00 |
|
Stefan Frederik
|
a2b0718a7a
|
added some symbols
|
2022-04-10 09:05:17 +02:00 |
|
Stefan Frederik
|
77be19bc6a
|
ind.sym artwork
|
2022-02-21 00:20:21 +01:00 |
|
Stefan Frederik
|
2e8bd72faf
|
reverted xcb since text quality is slightly better
|
2022-01-18 03:37:54 +01:00 |
|
Stefan Frederik
|
19398e8162
|
update window title/icon title when switching in tabbed interface
|
2022-01-10 03:00:33 +01:00 |
|
Stefan Frederik
|
756a7ba06d
|
swap s/d in verilog netlisting rule for enhancement load "rnmos4.sym" so it can be used as usually done with nmos devices (drain side up) .
|
2021-12-01 15:53:14 +01:00 |
|
Stefan Frederik
|
dcb37ef295
|
added devices/rnmos4.sym for enhancement load nmos gate simulation in verilog, updated test_mos_verilog.sch example
|
2021-12-01 14:25:27 +01:00 |
|
Stefan Frederik
|
39a27e856e
|
fix pcb_current_protection_embed.sch with up to date embedded symbols (previous had very old symbols with errors), fix pmos.sym (make pin names and verilog_format string consistent). All other schematics with embedded symbols updated with current library symbol. Some code in place for saving/restoring symbols in in-memory undo. This code is not compiled so does not affect xschem operation at all.
|
2021-11-25 04:00:01 +01:00 |
|
Stefan Frederik
|
7f9ee9fc2a
|
add "xschem check_symbols" and "xschem reload_symbols" for future checking of symbols that are newer wrt to schematic. set mtime of newly created schematic (that does not exist on disk) to current time. Add verilog attributes to devices/pmos4.sym
|
2021-11-21 12:28:36 +01:00 |
|
Stefan Frederik
|
0e91351e4a
|
fix depletion mos example
|
2021-11-21 01:18:12 +01:00 |
|
Stefan Frederik
|
64586f0c2d
|
depletion nmos transistor drawn with drain side low as this is the way it is used
|
2021-11-21 00:02:48 +01:00 |
|
Stefan Frederik
|
10114ec838
|
add missing braces in update recent file submenu, fix file selector improperly setting main window title, added logic/test_mos_verilog.sch depletion mode verilog example
|
2021-11-20 23:44:19 +01:00 |
|
Stefan Frederik
|
ebf0f0cf95
|
fixed simulation engine, no more bidirectional devices allowed
|
2021-10-30 03:12:06 +02:00 |
|
Stefan Frederik
|
0070498eb4
|
avoid printing "**** end_element" in spice netlist if current instance is skipped (no format or spice_ignore set); spice_probe_vdiff.sym will print .save v(n1) v(n2) instead of .save v(n1,n2) since this is how ngspice saves nodes (no differential voltage is saved)
|
2021-10-21 00:00:54 +02:00 |
|
Stefan Frederik
|
e8e56aa025
|
mux simulation operator: set "X" instead of "Z" if select not "0" or "1"
|
2021-09-27 10:56:23 +02:00 |
|
Stefan Frederik
|
f00b27d97d
|
interrupting xschem digital simulation with "Simulation->Forced stop tcl scripts" was leaving "tclstop" variable set, causing following simulation to produce erroneousr results. Any new sim resets the flag to 0.
|
2021-09-25 16:16:30 +02:00 |
|
Stefan Frederik
|
96c84c15f9
|
added conn_6x1.sym in devices
|
2021-09-25 01:49:42 +02:00 |
|
Stefan Frederik
|
975b1900dc
|
bus_connect_nolab.sym type set to "show_label" so it will be highlighted when net is highlighted, without needing to set "auto-highlight nets/pins".
|
2021-02-10 00:49:46 +01:00 |
|
Stefan Frederik
|
cea1069656
|
add "mux", "tristate" functions to logic expressions
|
2021-01-10 12:53:10 +01:00 |
|
Stefan Frederik
|
d64c8abb40
|
add -pg also in LDFLAGS if --profile is requested; add little more margin in ps page exports
|
2021-01-06 00:12:04 +01:00 |
|
Stefan Frederik
|
cc993bfe44
|
added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements)
|
2021-01-02 20:33:34 +01:00 |
|
Stefan Frederik
|
1fe6508704
|
ngspice_probe type set from "probe" to "ngprobe" to avoid clashes
|
2021-01-02 19:44:01 +01:00 |
|
Stefan Frederik
|
3528634124
|
Add Shift-Delete command that selects all nets/labels/probes physically attached to current selected wire segment/label/pin/probe
|
2021-01-02 18:56:42 +01:00 |
|
Stefan Frederik
|
73045ec1cb
|
example schematic updated and improvements
|
2021-01-01 04:24:57 +01:00 |
|
Stefan Frederik
|
14ead18ea4
|
"propagate_to" attribute for pins renamed to "goto"
|
2020-12-30 21:26:58 +01:00 |
|
Stefan Frederik
|
880286bdb9
|
update examples and ngspice_get_value.sym (@descr attribute)
|
2020-12-28 23:18:13 +01:00 |
|
Stefan Frederik
|
c897f230ce
|
update label display in ngspice_get_value.sym
|
2020-12-28 20:42:44 +01:00 |
|
Stefan Frederik
|
b71199c5b8
|
added "xschem_simulator" sample example directory for trying logic propagation of probed nets
|
2020-12-26 19:26:33 +01:00 |
|
Stefan Frederik
|
1cfea4d1d3
|
svg_draw(): do not print unused layer stylesheets, error check when opening file for printing
|
2020-12-22 18:31:08 +01:00 |
|
Stefan Frederik
|
2e18119645
|
remove "m=1" in xyce spice netlists as xyce does not handle m param. Translate spice_probe ".save" to xyce ".print tran", handle different hierarchical expansion of voltage/current nodes in xyce for hierarchical ammeter/spice_probe probes
|
2020-12-17 18:26:46 +01:00 |
|
Stefan Frederik
|
eb2d143e77
|
more consistent get_tok_value() regarding escaping
|
2020-11-29 01:59:17 +01:00 |
|
Stefan Frederik
|
9c5739b0f2
|
allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example
|
2020-11-24 02:54:45 +01:00 |
Stefan Schippers
|
bf183f0d20
|
Option (default now) to export svg images using the svg <text> element. This makes generated SVGs much smaller and in most cases faster to render.
|
2020-11-18 18:29:14 +01:00 |
|
Stefan Schippers
|
292958e4a2
|
added res_ac.sym
|
2020-11-06 19:43:26 +01:00 |
|
Stefan Schippers
|
191b4d8ed3
|
added m parameter to npn.sym and pnp.sym, text attribute edit dialog box renamed from .t to .dialog so it will be always raised on top of xschem window
|
2020-11-06 19:29:09 +01:00 |
|
Stefan Schippers
|
d5ff835614
|
sqwsource: do not use tcleval, leave the simple expressions parsing to the simulator
|
2020-10-26 02:58:29 +01:00 |
|
Stefan Schippers
|
460ebe561d
|
sqwsource.sym: better labels, various fixes, comments and more debug messages in tcleval() stuff, some fixes (error checks) in "device_model" related model_name() function
|
2020-10-25 03:03:23 +01:00 |
|
Stefan Schippers
|
7e845db5df
|
exampels/poweramp.sch and examples/cmos_example.sch show how to use dynamuc ngspice simulation data backannotation, optimized fix of previous bbox bug
|
2020-10-20 19:48:59 +02:00 |
|
Stefan Schippers
|
3bbba8601f
|
added ngspiec_probe.sym and ngspice_get_value.sym that use a pull method to fetch values from ngspice .raw datafile, fixed a long standing bug that changed bounding boxes of symbols that were selected for a copy if they were copied and copy operation involved rotations of flips.
|
2020-10-20 12:44:10 +02:00 |
|
Stefan Schippers
|
72e45216c2
|
spice_probe_dynamic.sym added to devices, retrieves node voltages with a pull method, so always updated, "@@pin" syntax in translate(), same as in format string for netlisting,print hilight nodes (ctrl-alt-j) will print .save instructions if netlist mode set to spice
|
2020-10-20 01:05:40 +02:00 |
|
Stefan Schippers
|
c84d71b859
|
xschem setprop made way faster if "fast" argument is provided. Example "clear probes" launcher object in mos_power_ampli.sch.
|
2020-10-19 02:07:17 +02:00 |
|
Stefan Schippers
|
7360982d7c
|
removed some redundant calls in prepare_netlist_structs(), no full instance spatial rehash if adding a component, set template name initials for components in devices/ that do not map directly to spice elements to lowercase letters.
|
2020-10-18 23:58:40 +02:00 |
|
Stefan Schippers
|
8a45e319c9
|
if xschem is started with -n (netlist) load_schematic will not call tcl proc is_xschem_file to determine if sch or sym type, since command line option has higher priority. reverted back possibility in update_symbol() to have double quotes around name attribute (name="My strange name"). This has toooo many implications everywhere. name attribute must be wihout double quotes, xschem will strip them off if any.
|
2020-10-17 02:54:42 +02:00 |
|
Stefan Schippers
|
0f94bee28e
|
better text positioning (net_name) on some devices/ symbols
|
2020-10-17 01:07:18 +02:00 |
|
Stefan Schippers
|
35c2d0fa93
|
better node multiplicity detection in spice and verilog awk netlist post-processors (\?-?[0-9]+)
|
2020-10-16 00:13:39 +02:00 |
|
Stefan Schippers
|
e82f270f61
|
replaced @ character with ? for spice netlist node multiplicity tags, so translate() will not try to expand them, do not print erc warnings for "non electrical" symbols (architecture, package, port_attributes, use, etc), print_spice_element() result string will be forwarded to translate() if enclosed within tcleval(...), so all @vars will be expanded. translate() in turn will forward to tcl_hook() if necessary.
|
2020-10-14 23:15:05 +02:00 |