From fb2500c83fe8dd5c31ed39ef68fc5b948774ed36 Mon Sep 17 00:00:00 2001 From: stefan schippers Date: Thu, 13 Apr 2023 02:12:02 +0200 Subject: [PATCH] enable spice_sym_def, verilog_sym_def, vhdl_sym_def on instances in addition as globally on symbols, for instance based specific implementations. These attributes must be paired with an instance "schematic=..." attribute that sets the subcircuit name of the alternate implementation. docs updated. --- doc/xschem_man/component_property_syntax.html | 31 ++++++++++++++++++- src/actions.c | 23 +++++++++++++- 2 files changed, 52 insertions(+), 2 deletions(-) diff --git a/doc/xschem_man/component_property_syntax.html b/doc/xschem_man/component_property_syntax.html index 528a1b02..7c3948c0 100644 --- a/doc/xschem_man/component_property_syntax.html +++ b/doc/xschem_man/component_property_syntax.html @@ -144,6 +144,35 @@ name="mchanged_name" model=\"nmos\" w="20u" l="3u" m="10"

This tells XSCHEM that for Verilog netlist this component will be completely ignored.

  • vhdl_ignore

    • This tells XSCHEM that for VHDL netlist this component will be completely ignored.

    + + +
  • spice_sym_def
    • +
  • verilog_sym_def
    • +
  • vhdl_sym_def
    • +

    If any of these attributes are present and not empty and the symbol type is set to subcircuit + the corresponding netlister will ignore the schematic subcircuit for this specific instance + and dump into the netlist the content of this attribute. + This attribute must be paired with a schematic=... attribute set on the instance that tells + the subcircuit name to use for this particular instance. + The typical usage is to include a file, example:
    + 

    +    verilog_sym_def="tcleval(`include \"[abs_sym_path verilog_include_file.v]\")"
+
    +

    +

    + In this example a verilog_include_file.v is included using the verilog `include directive. + In order to generate a full path for it the abs_sym_path TCL function is used that searches for this file + in any of the XCHEM_LIBRARY_PATH directories. Since TCL is used the attribute is wrappend into a tcleval(...),
    + The following will appear in the generated netlist: + 

    +// expanding   symbol:  verilog_include.sym # of pins=3 
+// sym_path: /home/schippes/.xschem/xschem_library/verilog_include.sym
+`include "/home/schippes/.xschem/xschem_library/verilog_include_file.v"
+
    +

    + + +
  • sig_type

    • For VHDL type netlist, this tells that the current label names a signal (or constant) of type sig_type. For example a label can be placed with name TEST and @@ -185,7 +214,7 @@ name="mchanged_name" model=\"nmos\" w="20u" l="3u" m="10" instance of a given subcircuit. The specified schematic must have the same interface (in/out/inout pins) as the base schematic (that is inferred from the symbol name).
    - Example: schematic=sky130_tests/inv2.sym + Example: schematic=sky130_tests/inv2.sch

  • pinnumber(name)
    • diff --git a/src/actions.c b/src/actions.c index 2c0d41e5..563d6adc 100644 --- a/src/actions.c +++ b/src/actions.c @@ -1216,7 +1216,15 @@ void get_additional_symbols(int what) } /* handle instances with "schematic=..." attribute (polymorphic symbols) */ for(i=0;iinstances; ++i) { - const char *sch = get_tok_value(xctx->inst[i].prop_ptr,"schematic",0); + char *spice_sym_def = NULL; + char *vhdl_sym_def = NULL; + char *verilog_sym_def = NULL; + const char *sch; + + my_strdup(_ALLOC_ID_, &spice_sym_def, get_tok_value(xctx->inst[i].prop_ptr,"spice_sym_def",0)); + my_strdup(_ALLOC_ID_, &verilog_sym_def, get_tok_value(xctx->inst[i].prop_ptr,"verilog_sym_def",0)); + my_strdup(_ALLOC_ID_, &vhdl_sym_def, get_tok_value(xctx->inst[i].prop_ptr,"vhdl_sym_def",0)); + sch = get_tok_value(xctx->inst[i].prop_ptr,"schematic",0); if(xctx->tok_size) { /* token exists */ const char *sym = add_ext(rel_sym_path(sch), ".sym"); int j; @@ -1228,11 +1236,24 @@ void get_additional_symbols(int what) check_symbol_storage(); copy_symbol(&xctx->sym[j], xctx->inst[i].ptr + xctx->sym); my_strdup(_ALLOC_ID_, &xctx->sym[j].name, sym); + + if(spice_sym_def) + my_strdup(_ALLOC_ID_, &xctx->sym[j].prop_ptr, + subst_token(xctx->sym[j].prop_ptr, "spice_sym_def", spice_sym_def)); + if(verilog_sym_def) + my_strdup(_ALLOC_ID_, &xctx->sym[j].prop_ptr, + subst_token(xctx->sym[j].prop_ptr, "verilog_sym_def", verilog_sym_def)); + if(vhdl_sym_def) + my_strdup(_ALLOC_ID_, &xctx->sym[j].prop_ptr, + subst_token(xctx->sym[j].prop_ptr, "vhdl_sym_def", vhdl_sym_def)); xctx->symbols++; } else { j = found->value; } } + my_free(_ALLOC_ID_, &spice_sym_def); + my_free(_ALLOC_ID_, &vhdl_sym_def); + my_free(_ALLOC_ID_, &verilog_sym_def); } int_hash_free(&sym_table); } else { /* end */