diff --git a/src/editprop.c b/src/editprop.c
index 2281c8e2..06a52578 100644
--- a/src/editprop.c
+++ b/src/editprop.c
@@ -1072,7 +1072,6 @@ void update_symbol(const char *result, int x)
       bbox(ADD, xctx->inst[*ii].x1, xctx->inst[*ii].y1,
                 xctx->inst[*ii].x2, xctx->inst[*ii].y2);
       if((s_pnetname || xctx->hilight_nets) && type && IS_LABEL_OR_PIN(type)) {
-        /* <<< do only .node[0] ? */
         for(j = 0;  j < (xctx->inst[*ii].ptr + xctx->sym)->rects[PINLAYER]; j++) {
           if( xctx->inst[*ii].node && xctx->inst[*ii].node[j]) {
              int_hash_lookup(xctx->node_redraw_table,  xctx->inst[*ii].node[j], 0, XINSERT_NOREPLACE);
diff --git a/src/in_memory_undo.c b/src/in_memory_undo.c
index 2f291f28..5c96585d 100644
--- a/src/in_memory_undo.c
+++ b/src/in_memory_undo.c
@@ -139,7 +139,7 @@ void clear_undo(void)
   xctx->cur_undo_ptr = 0;
   xctx->tail_undo_ptr = 0;
   xctx->head_undo_ptr = 0;
-  if(!xctx->initialized) return;
+  if(!xctx->undo_initialized) return;
   for(slot=0; slot<MAX_UNDO; slot++) {
     free_lines(slot);
     free_rects(slot);
@@ -174,8 +174,8 @@ void push_undo(void)
   int slot, i, c;
 
   if(xctx->no_undo)return;
-  if(!xctx->initialized) {
-    xctx->initialized=1;
+  if(!xctx->undo_initialized) {
+    xctx->undo_initialized=1;
     init_undo();
   }
   slot = xctx->cur_undo_ptr%MAX_UNDO;
@@ -288,7 +288,9 @@ void push_undo(void)
 
 /* BUG: in_memory_undo does not save/restore embedded symbols, it just saves references to symbols
  * if symbols are not found in library you get a schematic with missing symbols if you remove 
- * symbols and do an undo (this is done in netlist operations to purge unused syms */
+ * symbols and do an undo (this is done in netlist operations to purge unused syms
+ * if symbols are found in library your schematic will be linked with library symbols and this
+ * is not the intended behavior */
 
 /* redo:
  * 0: undo (with push current state for allowing following redo) 
diff --git a/src/save.c b/src/save.c
index c7063490..3ca32229 100644
--- a/src/save.c
+++ b/src/save.c
@@ -1007,11 +1007,13 @@ int save_schematic(const char *schname) /* 20171020 added return value */
     xctx->time_last_modify =  buf.st_mtime;
   }
   my_strncpy(xctx->current_name, rel_sym_path(name), S(xctx->current_name));
-  /* <<<<< >>>> why clear all these? */
-  xctx->prep_hi_structs=0;
-  xctx->prep_net_structs=0;
-  xctx->prep_hash_inst=0;
-  xctx->prep_hash_wires=0;
+  /* why clear all these? */
+  /* 
+   * xctx->prep_hi_structs=0;
+   * xctx->prep_net_structs=0;
+   * xctx->prep_hash_inst=0;
+   * xctx->prep_hash_wires=0;
+   */
   if(!strstr(xctx->sch[xctx->currsch], ".xschem_embedded_")) {
      set_modify(0);
   }
@@ -2208,7 +2210,8 @@ void make_schematic_symbol_from_sel(void)
     place_symbol(-1, filename, 0, 0, 0, 0, NULL, 4, 1, 0/*to_push_undo*/);
     if (has_x)
     {
-      my_snprintf(name, S(name), "tk_messageBox -type okcancel -message {do you want to make symbol view for %s ?}", filename);
+      my_snprintf(name, S(name), 
+        "tk_messageBox -type okcancel -message {do you want to make symbol view for %s ?}", filename);
       tcleval(name);
     }
     if (!has_x || !strcmp(tclresult(), "ok")) {
diff --git a/src/xinit.c b/src/xinit.c
index 37802d46..2380c9a0 100644
--- a/src/xinit.c
+++ b/src/xinit.c
@@ -583,7 +583,7 @@ void alloc_xschem_data(const char *top_path)
   xctx->fill_pattern = 1;
   xctx->draw_window = 0;
   #ifdef IN_MEMORY_UNDO
-  xctx->initialized = 0; /* in_memory_undo */
+  xctx->undo_initialized = 0; /* in_memory_undo */
   #endif
   xctx->time_last_modify = 0;
 }
diff --git a/src/xschem.h b/src/xschem.h
index a8a81351..fd31f761 100644
--- a/src/xschem.h
+++ b/src/xschem.h
@@ -437,7 +437,7 @@ typedef struct
    char *prop_ptr;
    char *type;
    char *templ;
-   int flags; /* bit 0: embedded flag 
+   int flags;   /* bit 0: embedded flag 
                  * bit 1: **free**
                  * bit 2: highight if connected wire highlighted */
 } xSymbol;
@@ -445,7 +445,7 @@ typedef struct
 typedef struct
 {
    char *name;/*  symbol name (ex: devices/lab_pin)  */
-   int ptr;  /*  was a pointer formerly... */
+   int ptr;   /*  was a pointer formerly... */
    double x0;  /* symbol origin / anchor point */
    double y0;
    double x1;  /* symbol bounding box */
@@ -678,7 +678,7 @@ typedef struct {
   #ifdef IN_MEMORY_UNDO
   /* in_memory_undo */
   Undo_slot uslot[MAX_UNDO];
-  int initialized;
+  int undo_initialized;
   #endif
   /*     */
   int nl_sel, nl_sem;
diff --git a/xschem_library/pcb/pcb_current_protection_embed.sch b/xschem_library/pcb/pcb_current_protection_embed.sch
index 81783c3a..0d2dd122 100644
--- a/xschem_library/pcb/pcb_current_protection_embed.sch
+++ b/xschem_library/pcb/pcb_current_protection_embed.sch
@@ -1,5 +1,6 @@
-v {xschem version=2.9.5_RC5 file_version=1.1}
+v {xschem version=3.0.0 file_version=1.2 }
 G {}
+K {}
 V {}
 S {}
 E {}
@@ -24,7 +25,7 @@ N 550 -320 650 -320 {lab=G}
 N 550 -260 650 -260 {lab=#net1}
 C {conn_3x1.sym} 150 -360 0 0 {name=C1 embed=true}
 [
-v {xschem version=2.9.5_RC5 file_version=1.1}
+v {xschem version=3.0.0 file_version=1.2}
 G {type=connector
 format="*connector(3,1) @pinlist"
 tedax_format="footprint @name @footprint"
@@ -47,7 +48,7 @@ P 4 5 10 30 -10 30 -10 -30 10 -30 10 30 {}
 ]
 C {vdd.sym} 770 -490 0 0 {name=l6 lab=VCC embed=true}
 [
-v {xschem version=2.9.5_RC5 file_version=1.1}
+v {xschem version=3.0.0 file_version=1.2}
 G {type=label
 global=1
 format="*.alias @lab"
@@ -62,7 +63,7 @@ T {@lab} -12.5 -35 0 0 0.2 0.2 {}
 ]
 C {lab_pin.sym} 860 -300 0 1 {name=p0 lab=VOUT embed=true}
 [
-v {xschem version=2.9.5_RC5 file_version=1.1}
+v {xschem version=3.0.0 file_version=1.2}
 G {type=label
 format="*.alias @lab"
 template="name=l1 sig_type=std_logic lab=xxx"}
@@ -74,7 +75,7 @@ T {@lab} -7.5 -7.5 0 1 0.36 0.33 {}
 ]
 C {lab_wire.sym} 660 -360 0 0 {name=l9 lab=G embed=true}
 [
-v {xschem version=2.9.5_RC5 file_version=1.1}
+v {xschem version=3.0.0 file_version=1.2}
 G {type=label
 format="*.alias @lab"
 template="name=l1 sig_type=std_logic lab=xxx"}
@@ -87,7 +88,7 @@ T {@lab} -3.75 -18.75 0 1 0.33 0.27 {}
 C {res.sym} 770 -190 0 0 {name=Rload m=1 value=100 footprint=1206 device=resistor
 tedax_ignore=true embed=true}
 [
-v {xschem version=2.9.5_RC5 file_version=1.1}
+v {xschem version=3.0.0 file_version=1.2}
 G {type=resistor
 format="@name @pinlist @value m=@m"
 verilog_format="tran @name ( @#0 , @#1 ) ;"
@@ -121,7 +122,7 @@ T {@#1:pinnumber} -5 20 0 1 0.12 0.12 {}
 ]
 C {gnd.sym} 770 -130 0 0 {name=l10 lab=VSS embed=true}
 [
-v {xschem version=2.9.5_RC5 file_version=1.1}
+v {xschem version=3.0.0 file_version=1.2}
 G {type=label
 global=1
 format="*.alias @lab"
@@ -151,7 +152,7 @@ vvss vss 0 dc 0
 .save all
 " embed=true}
 [
-v {xschem version=2.9.5_RC5 file_version=1.1}
+v {xschem version=3.0.0 file_version=1.2}
 G {type=netlist_commands
 template="name=s1 only_toplevel=false value=blabla"
 tedax_ignore=true
@@ -183,7 +184,7 @@ T {@name} 15 -25 0 0 0.3 0.3 {}
 C {pnp.sym} 580 -390 0 0 {name=Q6 model=BC857 device=BC857 area=1 footprint=SOT23
 url="https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=2ahUKEwijlfagu4zfAhUN0xoKHTPBAb0QFjAAegQIAhAC&url=http%3A%2F%2Fwww.onsemi.com%2Fpub%2FCollateral%2FPN2907-D.PDF&usg=AOvVaw2wgr87fGZgGfBRhXzHGwZM" embed=true}
 [
-v {xschem version=2.9.5_RC5 file_version=1.1}
+v {xschem version=3.0.0 file_version=1.2}
 G {type=pnp
 format="@name @pinlist @model area=@area"
 tedax_format="footprint @name @footprint
@@ -208,7 +209,7 @@ P 4 4 0 -10 15 -15 5 -25 0 -10 {fill=true}
 ]
 C {zener.sym} 330 -190 2 0 {name=x3 model=BZX5V1 device=BZX5V1 area=1 footprint=acy(300) embed=true}
 [
-v {xschem version=2.9.5_RC5 file_version=1.1}
+v {xschem version=3.0.0 file_version=1.2}
 G {type=diode
 format="@name @pinlist @model"
 tedax_format="footprint @name @footprint
@@ -231,17 +232,187 @@ T {@#1:pinnumber} -5 20 0 1 0.12 0.12 {}
 P 4 4 -0 5 -10 -5 10 -5 -0 5 {fill=true}
 ]
 C {gnd.sym} 330 -130 0 0 {name=l13 lab=VSS embed=true}
+[
+v {xschem version=3.0.0 file_version=1.2}
+G {type=label
+global=1
+format="*.alias @lab"
+template="name=l1 lab=GND"}
+V {}
+S {}
+E {}
+L 4 0 0 0 12.5 {}
+L 4 -5 12.5 5 12.5 {}
+L 4 0 17.5 5 12.5 {}
+L 4 -5 12.5 0 17.5 {}
+B 5 -2.5 -2.5 2.5 2.5 {name=p dir=inout}
+T {@lab} 7.5 5 0 0 0.2 0.2 {}
+]
 C {res.sym} 330 -460 0 0 {name=R4 m=1 value=4.7K footprint=1206 device=resistor embed=true}
+[
+v {xschem version=3.0.0 file_version=1.2}
+G {type=resistor
+format="@name @pinlist @value m=@m"
+verilog_format="tran @name ( @#0 , @#1 ) ;"
+tedax_format="footprint @name @footprint
+value @name @value
+device @name @device"
+template="name=R0 m=1 value=1k footprint=1206 device=resistor"}
+V {}
+S {}
+E {}
+L 4 0 20 0 30 {}
+L 4 0 20 7.5 17.5 {}
+L 4 -7.5 12.5 7.5 17.5 {}
+L 4 -7.5 12.5 7.5 7.5 {}
+L 4 -7.5 2.5 7.5 7.5 {}
+L 4 -7.5 2.5 7.5 -2.5 {}
+L 4 -7.5 -7.5 7.5 -2.5 {}
+L 4 -7.5 -7.5 7.5 -12.5 {}
+L 4 -7.5 -17.5 7.5 -12.5 {}
+L 4 -7.5 -17.5 0 -20 {}
+L 4 0 -30 0 -20 {}
+L 4 2.5 -22.5 7.5 -22.5 {}
+L 4 5 -25 5 -20 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout goto=1 pinnumber=1}
+B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout goto=0 pinnumber=2}
+T {@name} 15 -18.75 0 0 0.2 0.2 {}
+T {@value} 15 -3.75 0 0 0.2 0.2 {}
+T {m=@m} 15 11.25 0 0 0.2 0.2 {}
+T {@#0:pinnumber} -5 -25 0 1 0.12 0.12 {}
+T {@#1:pinnumber} -5 20 0 1 0.12 0.12 {}
+]
 C {vdd.sym} 330 -490 0 0 {name=l14 lab=VCC embed=true}
+[
+v {xschem version=3.0.0 file_version=1.2}
+G {type=label
+global=1
+format="*.alias @lab"
+template="name=l1 lab=VDD"}
+V {}
+S {}
+E {}
+L 4 0 -20 0 0 {}
+L 4 -10 -20 10 -20 {}
+B 5 -2.5 -2.5 2.5 2.5 {name=p dir=inout verilog_type=wire}
+T {@lab} -12.5 -35 0 0 0.2 0.2 {}
+]
 C {vdd.sym} 600 -490 0 0 {name=l15 lab=VCC embed=true}
+[
+v {xschem version=3.0.0 file_version=1.2}
+G {type=label
+global=1
+format="*.alias @lab"
+template="name=l1 lab=VDD"}
+V {}
+S {}
+E {}
+L 4 0 -20 0 0 {}
+L 4 -10 -20 10 -20 {}
+B 5 -2.5 -2.5 2.5 2.5 {name=p dir=inout verilog_type=wire}
+T {@lab} -12.5 -35 0 0 0.2 0.2 {}
+]
 C {res.sym} 600 -190 0 0 {name=R5 m=1 value=470 footprint=1206 device=resistor embed=true}
+[
+v {xschem version=3.0.0 file_version=1.2}
+G {type=resistor
+format="@name @pinlist @value m=@m"
+verilog_format="tran @name ( @#0 , @#1 ) ;"
+tedax_format="footprint @name @footprint
+value @name @value
+device @name @device"
+template="name=R0 m=1 value=1k footprint=1206 device=resistor"}
+V {}
+S {}
+E {}
+L 4 0 20 0 30 {}
+L 4 0 20 7.5 17.5 {}
+L 4 -7.5 12.5 7.5 17.5 {}
+L 4 -7.5 12.5 7.5 7.5 {}
+L 4 -7.5 2.5 7.5 7.5 {}
+L 4 -7.5 2.5 7.5 -2.5 {}
+L 4 -7.5 -7.5 7.5 -2.5 {}
+L 4 -7.5 -7.5 7.5 -12.5 {}
+L 4 -7.5 -17.5 7.5 -12.5 {}
+L 4 -7.5 -17.5 0 -20 {}
+L 4 0 -30 0 -20 {}
+L 4 2.5 -22.5 7.5 -22.5 {}
+L 4 5 -25 5 -20 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout goto=1 pinnumber=1}
+B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout goto=0 pinnumber=2}
+T {@name} 15 -18.75 0 0 0.2 0.2 {}
+T {@value} 15 -3.75 0 0 0.2 0.2 {}
+T {m=@m} 15 11.25 0 0 0.2 0.2 {}
+T {@#0:pinnumber} -5 -25 0 1 0.12 0.12 {}
+T {@#1:pinnumber} -5 20 0 1 0.12 0.12 {}
+]
 C {gnd.sym} 600 -130 0 0 {name=l16 lab=VSS embed=true}
+[
+v {xschem version=3.0.0 file_version=1.2}
+G {type=label
+global=1
+format="*.alias @lab"
+template="name=l1 lab=GND"}
+V {}
+S {}
+E {}
+L 4 0 0 0 12.5 {}
+L 4 -5 12.5 5 12.5 {}
+L 4 0 17.5 5 12.5 {}
+L 4 -5 12.5 0 17.5 {}
+B 5 -2.5 -2.5 2.5 2.5 {name=p dir=inout}
+T {@lab} 7.5 5 0 0 0.2 0.2 {}
+]
 C {lab_wire.sym} 360 -390 0 0 {name=l0 lab=B embed=true}
+[
+v {xschem version=3.0.0 file_version=1.2}
+G {type=label
+format="*.alias @lab"
+template="name=l1 sig_type=std_logic lab=xxx"}
+V {}
+S {}
+E {}
+B 5 -1.25 -1.25 1.25 1.25 {name=p dir=in}
+T {@lab} -3.75 -18.75 0 1 0.33 0.27 {}
+]
 C {res.sym} 330 -340 0 0 {name=R2 m=1 value=510 footprint=1206 device=resistor embed=true}
+[
+v {xschem version=3.0.0 file_version=1.2}
+G {type=resistor
+format="@name @pinlist @value m=@m"
+verilog_format="tran @name ( @#0 , @#1 ) ;"
+tedax_format="footprint @name @footprint
+value @name @value
+device @name @device"
+template="name=R0 m=1 value=1k footprint=1206 device=resistor"}
+V {}
+S {}
+E {}
+L 4 0 20 0 30 {}
+L 4 0 20 7.5 17.5 {}
+L 4 -7.5 12.5 7.5 17.5 {}
+L 4 -7.5 12.5 7.5 7.5 {}
+L 4 -7.5 2.5 7.5 7.5 {}
+L 4 -7.5 2.5 7.5 -2.5 {}
+L 4 -7.5 -7.5 7.5 -2.5 {}
+L 4 -7.5 -7.5 7.5 -12.5 {}
+L 4 -7.5 -17.5 7.5 -12.5 {}
+L 4 -7.5 -17.5 0 -20 {}
+L 4 0 -30 0 -20 {}
+L 4 2.5 -22.5 7.5 -22.5 {}
+L 4 5 -25 5 -20 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout goto=1 pinnumber=1}
+B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout goto=0 pinnumber=2}
+T {@name} 15 -18.75 0 0 0.2 0.2 {}
+T {@value} 15 -3.75 0 0 0.2 0.2 {}
+T {m=@m} 15 11.25 0 0 0.2 0.2 {}
+T {@#0:pinnumber} -5 -25 0 1 0.12 0.12 {}
+T {@#1:pinnumber} -5 20 0 1 0.12 0.12 {}
+]
 C {pmos.sym} 750 -360 0 0 {name=M2 m=1 model=IRLML6402 device=IRLML6402 footprint=SOT23
 url="https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=2ahUKEwjs8pzxuozfAhWpz4UKHR4CDnMQFjAAegQIAhAC&url=https%3A%2F%2Fwww.infineon.com%2Fdgdl%2Firlml6402.pdf%3FfileId%3D5546d462533600a401535668c9822638&usg=AOvVaw21fCRax-ssVpLqDeGK8KiC" embed=true}
 [
-v {xschem version=2.9.5_RC5 file_version=1.1}
+v {xschem version=3.0.0 file_version=1.2}
 G {type=pmos
 format="x@name @pinlist @model m=@m"
 tedax_format="footprint @name @footprint
@@ -271,7 +442,7 @@ T {@#1:pinnumber} -20 6.25 0 1 0.12 0.12 {}
 ]
 C {led.sym} 650 -290 0 0 {name=x1 model=D1N5765 device=D1N5765 area=1 footprint=acy(300) embed=true}
 [
-v {xschem version=2.9.5_RC5 file_version=1.1}
+v {xschem version=3.0.0 file_version=1.2}
 G {type=diode
 format="@name @pinlist @model"
 tedax_format="footprint @name @footprint
@@ -299,7 +470,7 @@ P 4 4 -0 5 -10 -5 10 -5 -0 5 {fill=true}
 ]
 C {title.sym} 160 -30 0 0 {name=l2 author="Stefan" embed=true}
 [
-v {xschem version=2.9.5_RC5 file_version=1.1}
+v {xschem version=3.0.0 file_version=1.2}
 G {type=logo
 template="name=l1 author=\\"Stefan Schippers\\""
 verilog_ignore=true
@@ -318,12 +489,128 @@ T {SCHEM} 5 -25 0 0 1 1 {}
 P 5 13 5 -30 -25 0 5 30 -15 30 -35 10 -55 30 -75 30 -45 0 -75 -30 -55 -30 -35 -10 -15 -30 5 -30 {fill=true}
 ]
 C {lab_pin.sym} 170 -340 0 1 {name=p6 lab=VOUT embed=true}
+[
+v {xschem version=3.0.0 file_version=1.2}
+G {type=label
+format="*.alias @lab"
+template="name=l1 sig_type=std_logic lab=xxx"}
+V {}
+S {}
+E {}
+B 5 -1.25 -1.25 1.25 1.25 {name=p dir=in}
+T {@lab} -7.5 -7.5 0 1 0.36 0.33 {}
+]
 C {lab_pin.sym} 170 -360 0 1 {name=p7 lab=VSS embed=true}
+[
+v {xschem version=3.0.0 file_version=1.2}
+G {type=label
+format="*.alias @lab"
+template="name=l1 sig_type=std_logic lab=xxx"}
+V {}
+S {}
+E {}
+B 5 -1.25 -1.25 1.25 1.25 {name=p dir=in}
+T {@lab} -7.5 -7.5 0 1 0.36 0.33 {}
+]
 C {lab_pin.sym} 170 -380 0 1 {name=p8 lab=VCC embed=true}
+[
+v {xschem version=3.0.0 file_version=1.2}
+G {type=label
+format="*.alias @lab"
+template="name=l1 sig_type=std_logic lab=xxx"}
+V {}
+S {}
+E {}
+B 5 -1.25 -1.25 1.25 1.25 {name=p dir=in}
+T {@lab} -7.5 -7.5 0 1 0.36 0.33 {}
+]
 C {zener.sym} 250 -190 2 0 {name=x4 model=BZX5V1 device=BZX5V1 area=1 footprint=minimelf spice_ignore=true embed=true}
+[
+v {xschem version=3.0.0 file_version=1.2}
+G {type=diode
+format="@name @pinlist @model"
+tedax_format="footprint @name @footprint
+device @name @device"
+template="name=x1 model=XXX device=XXX"}
+V {}
+S {}
+E {}
+L 4 0 5 0 30 {}
+L 4 0 -30 0 -5 {}
+L 4 -20 5 20 5 {}
+L 4 20 -5 20 5 {}
+L 4 -20 5 -20 15 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout pinnumber=1}
+B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout pinnumber=2}
+T {@name} 2.5 -20 0 0 0.2 0.2 {}
+T {@device} 2.5 12.5 0 0 0.2 0.2 {}
+T {@#0:pinnumber} -5 -25 0 1 0.12 0.12 {}
+T {@#1:pinnumber} -5 20 0 1 0.12 0.12 {}
+P 4 4 -0 5 -10 -5 10 -5 -0 5 {fill=true}
+]
 C {gnd.sym} 250 -130 0 0 {name=l1 lab=VSS embed=true}
+[
+v {xschem version=3.0.0 file_version=1.2}
+G {type=label
+global=1
+format="*.alias @lab"
+template="name=l1 lab=GND"}
+V {}
+S {}
+E {}
+L 4 0 0 0 12.5 {}
+L 4 -5 12.5 5 12.5 {}
+L 4 0 17.5 5 12.5 {}
+L 4 -5 12.5 0 17.5 {}
+B 5 -2.5 -2.5 2.5 2.5 {name=p dir=inout}
+T {@lab} 7.5 5 0 0 0.2 0.2 {}
+]
 C {res.sym} 550 -290 0 0 {name=R1 m=1 value=47K footprint=1206 device=resistor embed=true}
+[
+v {xschem version=3.0.0 file_version=1.2}
+G {type=resistor
+format="@name @pinlist @value m=@m"
+verilog_format="tran @name ( @#0 , @#1 ) ;"
+tedax_format="footprint @name @footprint
+value @name @value
+device @name @device"
+template="name=R0 m=1 value=1k footprint=1206 device=resistor"}
+V {}
+S {}
+E {}
+L 4 0 20 0 30 {}
+L 4 0 20 7.5 17.5 {}
+L 4 -7.5 12.5 7.5 17.5 {}
+L 4 -7.5 12.5 7.5 7.5 {}
+L 4 -7.5 2.5 7.5 7.5 {}
+L 4 -7.5 2.5 7.5 -2.5 {}
+L 4 -7.5 -7.5 7.5 -2.5 {}
+L 4 -7.5 -7.5 7.5 -12.5 {}
+L 4 -7.5 -17.5 7.5 -12.5 {}
+L 4 -7.5 -17.5 0 -20 {}
+L 4 0 -30 0 -20 {}
+L 4 2.5 -22.5 7.5 -22.5 {}
+L 4 5 -25 5 -20 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout goto=1 pinnumber=1}
+B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout goto=0 pinnumber=2}
+T {@name} 15 -18.75 0 0 0.2 0.2 {}
+T {@value} 15 -3.75 0 0 0.2 0.2 {}
+T {m=@m} 15 11.25 0 0 0.2 0.2 {}
+T {@#0:pinnumber} -5 -25 0 1 0.12 0.12 {}
+T {@#1:pinnumber} -5 20 0 1 0.12 0.12 {}
+]
 C {lab_wire.sym} 330 -260 0 0 {name=l3 lab=Z embed=true}
+[
+v {xschem version=3.0.0 file_version=1.2}
+G {type=label
+format="*.alias @lab"
+template="name=l1 sig_type=std_logic lab=xxx"}
+V {}
+S {}
+E {}
+B 5 -1.25 -1.25 1.25 1.25 {name=p dir=in}
+T {@lab} -3.75 -18.75 0 1 0.33 0.27 {}
+]
 C {code.sym} 950 -260 0 0 {name=MODELS 
 tedax_ignore=true
 only_toplevel=true
@@ -1504,3 +1791,33 @@ D2 8 6 DN
 V1 18 19 1.25
 .ENDS
 " tclcommand="xschem edit_vi_prop" embed=true}
+[
+v {xschem version=3.0.0 file_version=1.2}
+G {type=netlist_commands
+template="name=s1 only_toplevel=false value=blabla"
+tedax_ignore=true
+format="
+@value
+"}
+V {}
+S {}
+E {}
+L 3 20 30 60 30 {}
+L 3 20 40 40 40 {}
+L 3 20 50 60 50 {}
+L 3 20 60 50 60 {}
+L 3 20 70 50 70 {}
+L 3 20 80 90 80 {}
+L 3 20 90 40 90 {}
+L 3 20 20 70 20 {}
+L 3 20 10 40 10 {}
+L 5 100 10 110 10 {}
+L 5 110 10 110 110 {}
+L 5 20 110 110 110 {}
+L 5 20 100 20 110 {}
+L 5 100 0 100 100 {}
+L 5 10 100 100 100 {}
+L 5 10 0 10 100 {}
+L 5 10 0 100 0 {}
+T {@name} 15 -25 0 0 0.3 0.3 {}
+]