From f251918a0e99931f6bd4995535a31175e4604aa6 Mon Sep 17 00:00:00 2001
From: Stefan Frederik <stefan.schippers@gmail.com>
Date: Mon, 14 Jun 2021 00:35:20 +0200
Subject: [PATCH] fix usage of "xschem_libs", list of libraries/schematics NOT
 to netlist / export

---
 src/netlist.c         |  2 +-
 src/spice_netlist.c   | 14 ++++++++++----
 src/tedax_netlist.c   |  5 ++++-
 src/verilog_netlist.c |  5 ++++-
 src/vhdl_netlist.c    | 14 +++++++++++---
 5 files changed, 30 insertions(+), 10 deletions(-)

diff --git a/src/netlist.c b/src/netlist.c
index 2e005f28..46077341 100644
--- a/src/netlist.c
+++ b/src/netlist.c
@@ -367,7 +367,7 @@ int check_lib(const char *s)
  for(i=0;i<range;i++){
   my_snprintf(str, S(str), "lindex $xschem_libs %d",i);
   tcleval(str);
-  dbg(1, "check_lib(): xschem_libs=%s\n", tclresult());
+  dbg(1, "check_lib(): s=%s, xschem_libs=%s\n", s, tclresult());
   if( strstr(s,tclresult())) found=1;
  }
  if(found) return 0;
diff --git a/src/spice_netlist.c b/src/spice_netlist.c
index 96e3aeab..c3118e29 100644
--- a/src/spice_netlist.c
+++ b/src/spice_netlist.c
@@ -35,6 +35,7 @@ void hier_psprint(void)  /* netlister driver */
  char *subckt_name;
  int spice_stop;
  char filename[PATH_MAX];
+ char *abs_path = NULL;
  const char *str_tmp;
 
  if(!ps_draw(1)) return; /* prolog */
@@ -47,7 +48,7 @@ void hier_psprint(void)  /* netlister driver */
  free_hash(subckt_table);
  zoom_full(0, 0, 1, 0.97);
  ps_draw(2); /* page */
- dbg(0,"--> %s\n", skip_dir( xctx->sch[xctx->currsch]) );
+ dbg(1,"--> %s\n", skip_dir( xctx->sch[xctx->currsch]) );
  unselect_all();
  remove_symbols(); /* 20161205 ensure all unused symbols purged before descending hierarchy */
  load_schematic(1, xctx->sch[xctx->currsch], 0);
@@ -61,7 +62,8 @@ void hier_psprint(void)  /* netlister driver */
  {
   if( strcmp(get_tok_value(xctx->sym[i].prop_ptr,"spice_ignore",0),"true")==0 ) continue;
   if(!xctx->sym[i].type) continue;
-  if(strcmp(xctx->sym[i].type,"subcircuit")==0 && check_lib(abs_sym_path(xctx->sym[i].name, "")))
+  my_strdup(1230, &abs_path, abs_sym_path(xctx->sym[i].name, ""));
+  if(strcmp(xctx->sym[i].type,"subcircuit")==0 && check_lib(abs_path))
   {
     /* xctx->sym can be SCH or SYM, use hash to avoid writing duplicate subckt */
     my_strdup(1228, &subckt_name, get_cell(xctx->sym[i].name, 0));
@@ -82,9 +84,10 @@ void hier_psprint(void)  /* netlister driver */
 
       zoom_full(0, 0, 1, 0.97);
       ps_draw(2); /* page */
-      dbg(0,"--> %s\n", skip_dir( xctx->sch[xctx->currsch]) );
+      dbg(1,"--> %s\n", skip_dir( xctx->sch[xctx->currsch]) );
     }
   }
+  my_free(1231, &abs_path);
  }
  free_hash(subckt_table);
  my_free(1229, &subckt_name);
@@ -112,6 +115,7 @@ void global_spice_netlist(int global)  /* netlister driver */
  char tcl_cmd_netlist[PATH_MAX + 100]; /* 20081211 overflow safe 20161122 */
  char cellname[PATH_MAX]; /* 20081211 overflow safe 20161122 */
  char *subckt_name;
+ char *abs_path = NULL;
 
  xctx->netlist_unconn_cnt=0; /* unique count of unconnected pins while netlisting */
  statusmsg("",2);  /* clear infowindow */
@@ -249,7 +253,8 @@ void global_spice_netlist(int global)  /* netlister driver */
    {
     if( strcmp(get_tok_value(xctx->sym[i].prop_ptr,"spice_ignore",0),"true")==0 ) continue;
     if(!xctx->sym[i].type) continue;
-    if(strcmp(xctx->sym[i].type,"subcircuit")==0 && check_lib(abs_sym_path(xctx->sym[i].name, "")))
+    my_strdup(1232, &abs_path, abs_sym_path(xctx->sym[i].name, ""));
+    if(strcmp(xctx->sym[i].type,"subcircuit")==0 && check_lib(abs_path))
     {
       /* xctx->sym can be SCH or SYM, use hash to avoid writing duplicate subckt */
       my_strdup(391, &subckt_name, get_cell(xctx->sym[i].name, 0));
@@ -265,6 +270,7 @@ void global_spice_netlist(int global)  /* netlister driver */
             spice_block_netlist(fd, i);
       }
     }
+    my_free(1233, &abs_path);
    }
    free_hash(subckt_table);
    my_free(944, &subckt_name);
diff --git a/src/tedax_netlist.c b/src/tedax_netlist.c
index 94740262..06226cf4 100644
--- a/src/tedax_netlist.c
+++ b/src/tedax_netlist.c
@@ -31,6 +31,7 @@ void global_tedax_netlist(int global)  /* netlister driver */
  char netl_filename[PATH_MAX]; /* overflow safe 20161122 */
  char tcl_cmd_netlist[PATH_MAX + 100]; /* 20081211 overflow safe 20161122 */
  char cellname[PATH_MAX]; /* 20081211 overflow safe 20161122 */
+ char *abs_path = NULL;
 
  if(xctx->modified) {
    save_ok = save_schematic(xctx->sch[xctx->currsch]);
@@ -102,10 +103,12 @@ void global_tedax_netlist(int global)  /* netlister driver */
    {
     if( strcmp(get_tok_value(xctx->sym[i].prop_ptr,"tedax_ignore",0),"true")==0 ) continue;
     if(!xctx->sym[i].type) continue;
-    if(strcmp(xctx->sym[i].type,"subcircuit")==0 && check_lib(abs_sym_path(xctx->sym[i].name, "")))
+    my_strdup(1236, &abs_path, abs_sym_path(xctx->sym[i].name, ""));
+    if(strcmp(xctx->sym[i].type,"subcircuit")==0 && check_lib(abs_path))
     {
       tedax_block_netlist(fd, i);
     }
+    my_free(1237, &abs_path);
    }
    /*clear_drawing(); */
    my_strncpy(xctx->sch[xctx->currsch] , "", S(xctx->sch[xctx->currsch]));
diff --git a/src/verilog_netlist.c b/src/verilog_netlist.c
index f660ec13..418748ad 100644
--- a/src/verilog_netlist.c
+++ b/src/verilog_netlist.c
@@ -38,6 +38,7 @@ void global_verilog_netlist(int global)  /* netlister driver */
  char *type=NULL;
  struct stat buf;
  char *subckt_name;
+ char *abs_path = NULL;
 
  xctx->netlist_unconn_cnt=0; /* unique count of unconnected pins while netlisting */
  statusmsg("",2);  /* clear infowindow */
@@ -293,7 +294,8 @@ void global_verilog_netlist(int global)  /* netlister driver */
    {
     if( strcmp(get_tok_value(xctx->sym[i].prop_ptr,"verilog_ignore",0),"true")==0 ) continue;
     if(!xctx->sym[i].type) continue;
-    if(strcmp(xctx->sym[i].type,"subcircuit")==0 && check_lib(abs_sym_path(xctx->sym[i].name, ""))) {
+    my_strdup(1234, &abs_path, abs_sym_path(xctx->sym[i].name, ""));
+    if(strcmp(xctx->sym[i].type,"subcircuit")==0 && check_lib(abs_path)) {
       /* xctx->sym can be SCH or SYM, use hash to avoid writing duplicate subckt */
       my_strdup(328, &subckt_name, get_cell(xctx->sym[i].name, 0));
       if (str_hash_lookup(subckt_table, subckt_name, "", XLOOKUP)==NULL)
@@ -308,6 +310,7 @@ void global_verilog_netlist(int global)  /* netlister driver */
             verilog_block_netlist(fd, i);
       }
     }
+    my_free(1235, &abs_path);
    }
    free_hash(subckt_table);
    my_free(1073, &subckt_name);
diff --git a/src/vhdl_netlist.c b/src/vhdl_netlist.c
index c4a24930..149c3f02 100644
--- a/src/vhdl_netlist.c
+++ b/src/vhdl_netlist.c
@@ -38,6 +38,7 @@ void global_vhdl_netlist(int global)  /* netlister driver */
  char *type=NULL;
  struct stat buf;
  char *subckt_name;
+ char *abs_path = NULL;
 
  xctx->netlist_unconn_cnt=0; /* unique count of unconnected pins while netlisting */
  statusmsg("",2);  /* clear infowindow */
@@ -249,10 +250,11 @@ void global_vhdl_netlist(int global)  /* netlister driver */
   if( strcmp(get_tok_value(xctx->sym[j].prop_ptr,"vhdl_ignore",0),"true")==0 ) continue;
   if(!xctx->sym[j].type || (strcmp(xctx->sym[j].type,"primitive")!=0 &&
      strcmp(xctx->sym[j].type,"subcircuit")!=0)) continue;
+  my_strdup(1240, &abs_path, abs_sym_path(xctx->sym[j].name, ""));
   if((
       strcmp(xctx->sym[j].type,"subcircuit")==0 ||
       strcmp(xctx->sym[j].type,"primitive")==0
-     ) && check_lib(abs_sym_path(xctx->sym[j].name, ""))
+     ) && check_lib(abs_path)
     )
   {
    /* xctx->sym can be SCH or SYM, use hash to avoid writing duplicate subckt */
@@ -288,6 +290,7 @@ void global_vhdl_netlist(int global)  /* netlister driver */
      fprintf(fd, "end component ;\n\n");
    }
   }
+  my_free(1241, &abs_path);
  }
  free_hash(subckt_table);
  my_free(1086, &subckt_name);
@@ -345,7 +348,8 @@ void global_vhdl_netlist(int global)  /* netlister driver */
    {
     if( strcmp(get_tok_value(xctx->sym[i].prop_ptr,"vhdl_ignore",0),"true")==0 ) continue;
     if(!xctx->sym[i].type) continue;
-    if(strcmp(xctx->sym[i].type,"subcircuit")==0 && check_lib(abs_sym_path(xctx->sym[i].name, "")))
+    my_strdup(1242, &abs_path, abs_sym_path(xctx->sym[j].name, ""));
+    if(strcmp(xctx->sym[i].type,"subcircuit")==0 && check_lib(abs_path))
     {
       /* xctx->sym can be SCH or SYM, use hash to avoid writing duplicate subckt */
       my_strdup(327, &subckt_name, get_cell(xctx->sym[i].name, 0));
@@ -361,6 +365,7 @@ void global_vhdl_netlist(int global)  /* netlister driver */
             vhdl_block_netlist(fd, i);
       }
     }
+    my_free(1243, &abs_path);
    }
    free_hash(subckt_table);
    my_free(1087, &subckt_name);
@@ -413,6 +418,7 @@ void  vhdl_block_netlist(FILE *fd, int i)
   char tcl_cmd_netlist[PATH_MAX + 100];
   char cellname[PATH_MAX];
   const char *str_tmp;
+  char *abs_path = NULL;
 
   if(!strcmp( get_tok_value(xctx->sym[i].prop_ptr,"vhdl_stop",0),"true") )
     vhdl_stop=1;
@@ -525,8 +531,9 @@ void  vhdl_block_netlist(FILE *fd, int i)
       if(!xctx->sym[j].type || (strcmp(xctx->sym[j].type,"primitive")!=0 && 
          strcmp(xctx->sym[j].type,"subcircuit")!=0))
            continue;
+      my_strdup(1238, &abs_path, abs_sym_path(xctx->sym[i].name, ""));
       if(( strcmp(xctx->sym[j].type,"subcircuit")==0 || strcmp(xctx->sym[j].type,"primitive")==0) && 
-          check_lib(abs_sym_path(xctx->sym[j].name, ""))
+          check_lib(abs_path)
         ) {
  
         /* only print component declaration if used in current subcircuit */
@@ -573,6 +580,7 @@ void  vhdl_block_netlist(FILE *fd, int i)
         if(tmp) fprintf(fd, "\n);\n");
         fprintf(fd, "end component ;\n\n");
       }
+      my_free(1239, &abs_path);
     }
   dbg(1, "vhdl_block_netlist():  netlisting %s\n", skip_dir( xctx->sch[xctx->currsch]));
   vhdl_netlist(fd, vhdl_stop);