From e5205cfd1e13e9504610c5d4edb6d3130f6561fb Mon Sep 17 00:00:00 2001 From: Stefan Frederik Date: Fri, 4 Dec 2020 12:45:50 +0100 Subject: [PATCH] Split mode netlisting in different formats got bitrotten due to a regression. Fixed. --- src/netlist.c | 17 ++++++++++++++ src/spice_netlist.c | 4 ++++ src/verilog_netlist.c | 4 ++++ src/vhdl_netlist.c | 4 ++++ src/xschem.h | 1 + src/xschem.tcl | 25 +++++++++++---------- xschem_library/examples/mos_power_ampli.sym | 3 ++- 7 files changed, 45 insertions(+), 13 deletions(-) diff --git a/src/netlist.c b/src/netlist.c index c6ea9b0a..03fab15a 100644 --- a/src/netlist.c +++ b/src/netlist.c @@ -601,6 +601,23 @@ int record_global_node(int what, FILE *fp, char *node) return 0; } +/* set netlist_type tcl var to specified format, if -1 is given restore to default */ +void override_netlist_type(int type) +{ + if (type == CAD_VHDL_NETLIST) tclsetvar("netlist_type","vhdl"); + else if(type == CAD_VERILOG_NETLIST) tclsetvar("netlist_type","verilog"); + else if(type == CAD_TEDAX_NETLIST) tclsetvar("netlist_type","tedax"); + else if(type == CAD_SYMBOL_ATTRS) tclsetvar("netlist_type","symbol"); + else if(type == CAD_SPICE_NETLIST) tclsetvar("netlist_type","spice"); + else { + if (netlist_type == CAD_VHDL_NETLIST) tclsetvar("netlist_type","vhdl"); + else if(netlist_type == CAD_VERILOG_NETLIST) tclsetvar("netlist_type","verilog"); + else if(netlist_type == CAD_TEDAX_NETLIST) tclsetvar("netlist_type","tedax"); + else if(netlist_type == CAD_SYMBOL_ATTRS) tclsetvar("netlist_type","symbol"); + else if(netlist_type == CAD_SPICE_NETLIST) tclsetvar("netlist_type","spice"); + } +} + void prepare_netlist_structs(int for_netlist) { xRect *rct; diff --git a/src/spice_netlist.c b/src/spice_netlist.c index d5d00c02..8ea1cd9d 100644 --- a/src/spice_netlist.c +++ b/src/spice_netlist.c @@ -150,7 +150,9 @@ void global_spice_netlist(int global) /* netlister driver */ if(split_files) { fclose(fd); my_snprintf(tcl_cmd_netlist, S(tcl_cmd_netlist), "netlist {%s} noshow {%s}", netl_filename, cellname); + override_netlist_type(CAD_SPICE_NETLIST); tcleval(tcl_cmd_netlist); + override_netlist_type(-1); /* restore to netlist_type default */ if(debug_var==0) xunlink(netl_filename); } @@ -362,7 +364,9 @@ void spice_block_netlist(FILE *fd, int i) if(split_files) { fclose(fd); my_snprintf(tcl_cmd_netlist, S(tcl_cmd_netlist), "netlist {%s} noshow {%s}", netl_filename, cellname); + override_netlist_type(CAD_SPICE_NETLIST); tcleval(tcl_cmd_netlist); + override_netlist_type(-1); /* restore to netlist_type default */ if(debug_var==0) xunlink(netl_filename); } } diff --git a/src/verilog_netlist.c b/src/verilog_netlist.c index cc6bdbc1..a33c752e 100644 --- a/src/verilog_netlist.c +++ b/src/verilog_netlist.c @@ -263,7 +263,9 @@ void global_verilog_netlist(int global) /* netlister driver */ if(split_files) { fclose(fd); my_snprintf(tcl_cmd_netlist, S(tcl_cmd_netlist), "netlist {%s} noshow {%s}", netl_filename, cellname); + override_netlist_type(CAD_VERILOG_NETLIST); tcleval(tcl_cmd_netlist); + override_netlist_type(-1); /* restore to netlist_type default */ if(debug_var==0) xunlink(netl_filename); } @@ -486,7 +488,9 @@ void verilog_block_netlist(FILE *fd, int i) if(split_files) { fclose(fd); my_snprintf(tcl_cmd_netlist, S(tcl_cmd_netlist), "netlist {%s} noshow {%s}", netl_filename, cellname); + override_netlist_type(CAD_VERILOG_NETLIST); tcleval(tcl_cmd_netlist); + override_netlist_type(-1); /* restore to netlist_type default */ if(debug_var==0) xunlink(netl_filename); } my_free(1079, &dir_tmp); diff --git a/src/vhdl_netlist.c b/src/vhdl_netlist.c index 7a81c799..76c7b1f6 100644 --- a/src/vhdl_netlist.c +++ b/src/vhdl_netlist.c @@ -315,7 +315,9 @@ void global_vhdl_netlist(int global) /* netlister driver */ if(split_files) { fclose(fd); my_snprintf(tcl_cmd_netlist, S(tcl_cmd_netlist), "netlist {%s} noshow {%s}", netl_filename, cellname); + override_netlist_type(CAD_VHDL_NETLIST); tcleval(tcl_cmd_netlist); + override_netlist_type(-1); /* restore to netlist_dir default */ if(debug_var==0) xunlink(netl_filename); } netlist_count++; @@ -591,7 +593,9 @@ void vhdl_block_netlist(FILE *fd, int i) if(split_files) { fclose(fd); my_snprintf(tcl_cmd_netlist, S(tcl_cmd_netlist), "netlist {%s} noshow {%s}", netl_filename, cellname); + override_netlist_type(CAD_VHDL_NETLIST); tcleval(tcl_cmd_netlist); + override_netlist_type(-1); /* restore to netlist_dir default */ if(debug_var==0) xunlink(netl_filename); } netlist_count++; diff --git a/src/xschem.h b/src/xschem.h index 36a3d689..6b5ebd38 100644 --- a/src/xschem.h +++ b/src/xschem.h @@ -1056,6 +1056,7 @@ extern void unhilight_net(); extern void draw_hilight_net(int on_window); extern void display_hilights(char **str); extern void redraw_hilights(void); +extern void override_netlist_type(int type); extern void prepare_netlist_structs(int for_netlist); extern void delete_netlist_structs(void); extern void delete_inst_node(int i); diff --git a/src/xschem.tcl b/src/xschem.tcl index 87e65cbf..83c47078 100644 --- a/src/xschem.tcl +++ b/src/xschem.tcl @@ -111,8 +111,9 @@ proc execute {status args} { proc netlist {source_file show netlist_file} { global XSCHEM_SHAREDIR flat_netlist hspice_netlist netlist_dir - global verilog_2001 netlist_type + global verilog_2001 netlist_type tcl_debug + if {$tcl_debug <= 0} { puts "netlist: source_file=$source_file, netlist_type=$netlist_type" } if {$netlist_type eq {spice}} { if { $hspice_netlist == 1 } { set hspice {-hspice} @@ -1948,7 +1949,7 @@ proc property_search {} { button .dialog.but.ok -text OK -command { set search_value [.dialog.val.e get] set custom_token [.dialog.custom.e get] - if $tcl_debug<=-1 then { puts stderr "|$custom_token|" } + if {$tcl_debug<=-1} { puts stderr "|$custom_token|" } set token $custom_token if { $search_exact==1 } { xschem searchmenu exact $search_select $token $search_value @@ -2132,14 +2133,14 @@ proc edit_vi_prop {txtlabel} { set filename $filename.$suffix write_data $retval $XSCHEM_TMP_DIR/$filename eval execute_wait 0 $editor $XSCHEM_TMP_DIR/$filename ;# 20161119 - if $tcl_debug<=-1 then {puts "edit_vi_prop{}:\n--------\nretval=$retval\n---------\n"} - if $tcl_debug<=-1 then {puts "edit_vi_prop{}:\n--------\nsymbol=$symbol\n---------\n"} + if {$tcl_debug<=-1} {puts "edit_vi_prop{}:\n--------\nretval=$retval\n---------\n"} + if {$tcl_debug<=-1} {puts "edit_vi_prop{}:\n--------\nsymbol=$symbol\n---------\n"} set tmp [read_data $XSCHEM_TMP_DIR/$filename] file delete $XSCHEM_TMP_DIR/$filename - if $tcl_debug<=-1 then {puts "edit_vi_prop{}:\n--------\n$tmp\n---------\n"} + if {$tcl_debug<=-1} {puts "edit_vi_prop{}:\n--------\n$tmp\n---------\n"} if [string compare $tmp $retval] { set retval $tmp - if $tcl_debug<=-1 then {puts "modified"} + if {$tcl_debug<=-1} {puts "modified"} set rcode ok return $rcode } else { @@ -2161,15 +2162,15 @@ proc edit_vi_netlist_prop {txtlabel} { write_data $retval $XSCHEM_TMP_DIR/$filename if { [regexp vim $editor] } { set ftype "\{-c :set filetype=$netlist_type\}" } else { set ftype {} } eval execute_wait 0 $editor $ftype $XSCHEM_TMP_DIR/$filename - if $tcl_debug<=-1 then {puts "edit_vi_prop{}:\n--------\n$retval\n---------\n"} + if {$tcl_debug <= -1} {puts "edit_vi_prop{}:\n--------\n$retval\n---------\n"} set tmp [read_data $XSCHEM_TMP_DIR/$filename] file delete $XSCHEM_TMP_DIR/$filename - if $tcl_debug<=-1 then {puts "edit_vi_prop{}:\n--------\n$tmp\n---------\n"} + if {$tcl_debug <= -1} {puts "edit_vi_prop{}:\n--------\n$tmp\n---------\n"} if [string compare $tmp $retval] { set retval $tmp regsub -all {(["\\])} $retval {\\\1} retval ;#" editor is confused by the previous quote set retval \"${retval}\" - if $tcl_debug<=-1 then {puts "modified"} + if {$tcl_debug <= -1} {puts "modified"} set rcode ok return $rcode } else { @@ -2219,7 +2220,7 @@ proc edit_prop {txtlabel} { set user_wants_copy_cell 0 set rcode {} set retval_orig $retval - if $tcl_debug<=-1 then {puts " edit_prop{}: retval=$retval"} + if {$tcl_debug <= -1} {puts " edit_prop{}: retval=$retval"} if { [winfo exists .dialog] } return toplevel .dialog -class Dialog wm title .dialog {Edit Properties} @@ -2452,8 +2453,8 @@ proc text_line {txtlabel clear {preserve_disabled disabled} } { global retval rcode tcl_debug tok_list selected_tok retval_orig old_selected_tok set retval_orig $retval if $clear==1 then {set retval ""} - if $tcl_debug<=-1 then {puts " text_line{}: clear=$clear"} - if $tcl_debug<=-1 then {puts " text_line{}: retval=$retval"} + if {$tcl_debug <= -1} {puts " text_line{}: clear=$clear"} + if {$tcl_debug <= -1} {puts " text_line{}: retval=$retval"} set rcode {} if { [winfo exists .dialog] } return toplevel .dialog -class Dialog diff --git a/xschem_library/examples/mos_power_ampli.sym b/xschem_library/examples/mos_power_ampli.sym index 8c7363ca..14399ef0 100644 --- a/xschem_library/examples/mos_power_ampli.sym +++ b/xschem_library/examples/mos_power_ampli.sym @@ -3,7 +3,8 @@ G {} K {type=subcircuit format="@name @pinlist @symname" template="name=x1" -net_name=true} +net_name=true +verilog_netlist=true} V {} S {} E {}