From dfef332fb568a85b0b2a5e902a7be346b0dea35b Mon Sep 17 00:00:00 2001
From: Stefan Frederik <stefan.schippers@gmail.com>
Date: Sat, 12 Jun 2021 00:54:09 +0200
Subject: [PATCH] Replace *.ipin/*.opin/*.iopin info lines with *.PININFO....
 if LVS netlist is selected. Use absolute path of symbols in check_lib
 function. Make PNG export work if destination path contains spaces.

---
 src/netlist.c         |  2 +-
 src/spice_netlist.c   | 19 ++++++++++++++++---
 src/tedax_netlist.c   |  2 +-
 src/verilog_netlist.c |  2 +-
 src/vhdl_netlist.c    |  6 +++---
 src/xschem.h          |  2 +-
 src/xschem.tcl        | 16 ++++++++--------
 7 files changed, 31 insertions(+), 18 deletions(-)

diff --git a/src/netlist.c b/src/netlist.c
index b3605232..2e005f28 100644
--- a/src/netlist.c
+++ b/src/netlist.c
@@ -354,7 +354,7 @@ void hash_wires(void)
 }
 
 /* return 0 if library path of s matches any lib name in tcl variable $xschem_libs */
-int check_lib(char *s)
+int check_lib(const char *s)
 {
  int range,i, found;
  char str[200]; /* overflow safe 20161122 */
diff --git a/src/spice_netlist.c b/src/spice_netlist.c
index dd452013..b02556e6 100644
--- a/src/spice_netlist.c
+++ b/src/spice_netlist.c
@@ -177,7 +177,7 @@ void global_spice_netlist(int global)  /* netlister driver */
    {
     if( strcmp(get_tok_value(xctx->sym[i].prop_ptr,"spice_ignore",0),"true")==0 ) continue;
     if(!xctx->sym[i].type) continue;
-    if(strcmp(xctx->sym[i].type,"subcircuit")==0 && check_lib(xctx->sym[i].name))
+    if(strcmp(xctx->sym[i].type,"subcircuit")==0 && check_lib(abs_sym_path(xctx->sym[i].name, "")))
     {
       /* xctx->sym can be SCH or SYM, use hash to avoid writing duplicate subckt */
       my_strdup(391, &subckt_name, get_cell(xctx->sym[i].name, 0));
@@ -372,7 +372,7 @@ void spice_block_netlist(FILE *fd, int i)
 
 void spice_netlist(FILE *fd, int spice_stop )
 {
-  int i;
+  int i, flag = 0;
   char *type=NULL;
  
   if(!spice_stop) {
@@ -388,9 +388,22 @@ void spice_netlist(FILE *fd, int spice_stop )
      }
      my_strdup(388, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
      if( type && IS_PIN(type) ) {
-       print_spice_element(fd, i) ;  /* this is the element line  */
+       if(top_subckt && !flag) {
+         fprintf(fd, "*.PININFO ");
+         flag = 1;
+       }
+       if(top_subckt) {
+         int d;
+         if(!strcmp(type, "ipin")) d = 'I';
+         if(!strcmp(type, "opin")) d = 'O';
+         if(!strcmp(type, "iopin")) d = 'B';
+         fprintf(fd, "%s:%c ",get_tok_value(xctx->inst[i].prop_ptr, "lab",0), d);
+       } else {
+         print_spice_element(fd, i) ;  /* this is the element line  */
+       }
      }
     }
+    if(top_subckt) fprintf(fd, "\n");
     for(i=0;i<xctx->instances;i++) /* ... then print other lines */
     {
      if( strcmp(get_tok_value(xctx->inst[i].prop_ptr,"spice_ignore",0),"true")==0 ) continue;
diff --git a/src/tedax_netlist.c b/src/tedax_netlist.c
index e8477b2f..94740262 100644
--- a/src/tedax_netlist.c
+++ b/src/tedax_netlist.c
@@ -102,7 +102,7 @@ void global_tedax_netlist(int global)  /* netlister driver */
    {
     if( strcmp(get_tok_value(xctx->sym[i].prop_ptr,"tedax_ignore",0),"true")==0 ) continue;
     if(!xctx->sym[i].type) continue;
-    if(strcmp(xctx->sym[i].type,"subcircuit")==0 && check_lib(xctx->sym[i].name))
+    if(strcmp(xctx->sym[i].type,"subcircuit")==0 && check_lib(abs_sym_path(xctx->sym[i].name, "")))
     {
       tedax_block_netlist(fd, i);
     }
diff --git a/src/verilog_netlist.c b/src/verilog_netlist.c
index 977b6889..f660ec13 100644
--- a/src/verilog_netlist.c
+++ b/src/verilog_netlist.c
@@ -293,7 +293,7 @@ void global_verilog_netlist(int global)  /* netlister driver */
    {
     if( strcmp(get_tok_value(xctx->sym[i].prop_ptr,"verilog_ignore",0),"true")==0 ) continue;
     if(!xctx->sym[i].type) continue;
-    if(strcmp(xctx->sym[i].type,"subcircuit")==0 && check_lib(xctx->sym[i].name)) {
+    if(strcmp(xctx->sym[i].type,"subcircuit")==0 && check_lib(abs_sym_path(xctx->sym[i].name, ""))) {
       /* xctx->sym can be SCH or SYM, use hash to avoid writing duplicate subckt */
       my_strdup(328, &subckt_name, get_cell(xctx->sym[i].name, 0));
       if (str_hash_lookup(subckt_table, subckt_name, "", XLOOKUP)==NULL)
diff --git a/src/vhdl_netlist.c b/src/vhdl_netlist.c
index 27cfc4b8..c4a24930 100644
--- a/src/vhdl_netlist.c
+++ b/src/vhdl_netlist.c
@@ -252,7 +252,7 @@ void global_vhdl_netlist(int global)  /* netlister driver */
   if((
       strcmp(xctx->sym[j].type,"subcircuit")==0 ||
       strcmp(xctx->sym[j].type,"primitive")==0
-     ) && check_lib(xctx->sym[j].name)
+     ) && check_lib(abs_sym_path(xctx->sym[j].name, ""))
     )
   {
    /* xctx->sym can be SCH or SYM, use hash to avoid writing duplicate subckt */
@@ -345,7 +345,7 @@ void global_vhdl_netlist(int global)  /* netlister driver */
    {
     if( strcmp(get_tok_value(xctx->sym[i].prop_ptr,"vhdl_ignore",0),"true")==0 ) continue;
     if(!xctx->sym[i].type) continue;
-    if(strcmp(xctx->sym[i].type,"subcircuit")==0 && check_lib(xctx->sym[i].name))
+    if(strcmp(xctx->sym[i].type,"subcircuit")==0 && check_lib(abs_sym_path(xctx->sym[i].name, "")))
     {
       /* xctx->sym can be SCH or SYM, use hash to avoid writing duplicate subckt */
       my_strdup(327, &subckt_name, get_cell(xctx->sym[i].name, 0));
@@ -526,7 +526,7 @@ void  vhdl_block_netlist(FILE *fd, int i)
          strcmp(xctx->sym[j].type,"subcircuit")!=0))
            continue;
       if(( strcmp(xctx->sym[j].type,"subcircuit")==0 || strcmp(xctx->sym[j].type,"primitive")==0) && 
-          check_lib(xctx->sym[j].name)
+          check_lib(abs_sym_path(xctx->sym[j].name, ""))
         ) {
  
         /* only print component declaration if used in current subcircuit */
diff --git a/src/xschem.h b/src/xschem.h
index 47bde8b9..2a6b18ff 100644
--- a/src/xschem.h
+++ b/src/xschem.h
@@ -843,7 +843,7 @@ extern void here(int i);
 extern void print_version(void);
 extern int set_netlist_dir(int force, char *dir);
 extern void netlist_options(int i);
-extern int  check_lib(char * s);
+extern int  check_lib(const char * s);
 extern void select_all(void);
 extern void change_linewidth(double w);
 extern void schematic_in_new_window(void);
diff --git a/src/xschem.tcl b/src/xschem.tcl
index 904d21f1..fcf781f9 100644
--- a/src/xschem.tcl
+++ b/src/xschem.tcl
@@ -194,14 +194,14 @@ proc netlist {source_file show netlist_file} {
 # 20161121
 proc convert_to_pdf {filename dest} {
   global to_pdf
-  # puts "convert_to_pdf: $filename --> $dest"
   if { [regexp -nocase {\.pdf$} $dest] } {
     set pdffile [file rootname $filename].pdf
-    set cmd "exec $to_pdf $filename $pdffile"
+    # puts "---> $to_pdf $filename $pdffile"
+    set cmd "exec $to_pdf \$filename \$pdffile"
     if {$::OS == "Windows"} {
-      set cmd "exec $to_pdf $pdffile $filename"
+      set cmd "exec $to_pdf \$pdffile \$filename"
     } 
-    if { ![catch $cmd msg] } {
+    if { ![catch {eval $cmd} msg] } {
       file rename -force $pdffile $dest
       # ps2pdf succeeded, so remove original .ps file
       if { ![xschem get debug_var] } {
@@ -218,12 +218,12 @@ proc convert_to_pdf {filename dest} {
 # 20161121
 proc convert_to_png {filename dest} {
   global to_png tcl_debug
-  # puts "---> $to_png $filename $destfile"
-  set cmd "exec $to_png $filename png:$dest"
+  # puts "---> $to_png $filename $dest"
+  set cmd "exec $to_png \$filename png:\$dest"
     if {$::OS == "Windows"} {
-      set cmd "exec $to_png $dest $filename"
+      set cmd "exec $to_png \$dest \$filename"
     } 
-  if { ![catch $cmd msg] } {
+  if { ![catch {eval $cmd} msg] } {
     # conversion succeeded, so remove original .xpm file
     if { ![xschem get debug_var] } {
       file delete $filename