From dcb37ef295088b7076b525be1dfd239008740649 Mon Sep 17 00:00:00 2001
From: Stefan Frederik <stefan.schippers@gmail.com>
Date: Wed, 1 Dec 2021 14:25:27 +0100
Subject: [PATCH] added devices/rnmos4.sym for enhancement load nmos gate
 simulation in verilog, updated test_mos_verilog.sch example

---
 xschem_library/devices/nmos4_depl.sym     |  2 +-
 xschem_library/devices/rnmos4.sym         | 33 +++++++++++++++++++++++
 xschem_library/logic/test_mos_verilog.sch | 26 +++++++++++++++++-
 3 files changed, 59 insertions(+), 2 deletions(-)
 create mode 100644 xschem_library/devices/rnmos4.sym

diff --git a/xschem_library/devices/nmos4_depl.sym b/xschem_library/devices/nmos4_depl.sym
index 888fd0f8..902cd3a2 100644
--- a/xschem_library/devices/nmos4_depl.sym
+++ b/xschem_library/devices/nmos4_depl.sym
@@ -2,7 +2,7 @@ v {xschem version=3.0.0 file_version=1.2 }
 G {}
 K {type=nmos
 format="@spiceprefix@name @pinlist @model w=@w l=@l @extra m=@m"
-template="name=M1 model=nmos w=5u l=0.18u del=0 m=1"
+template="name=M1 model=nmos_depl w=5u l=0.18u del=0 m=1"
 verilog_format="rnmos #@del @name ( @@s , @@d , @@d );"}
 V {}
 S {}
diff --git a/xschem_library/devices/rnmos4.sym b/xschem_library/devices/rnmos4.sym
new file mode 100644
index 00000000..b2af66d9
--- /dev/null
+++ b/xschem_library/devices/rnmos4.sym
@@ -0,0 +1,33 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=nmos
+format="@spiceprefix@name @pinlist @model w=@w l=@l @extra m=@m"
+template="name=M1 model=nmos w=5u l=0.18u del=0 m=1"
+verilog_format="rnmos #@del @name ( @@d , @@s , @@g );"}
+V {}
+S {}
+E {}
+L 4 5 -30 5 30 {}
+L 4 5 -20 20 -20 {}
+L 4 20 -30 20 -20 {}
+L 4 5 20 20 20 {}
+L 4 20 20 20 30 {}
+L 4 -5 -15 -5 15 {}
+L 4 -5 0 -5 5 {}
+L 4 -20 0 -12.5 0 {}
+L 4 -20 0 -5 0 {}
+L 4 15 0 20 0 {}
+L 4 10 -5 15 0 {}
+L 4 10 5 15 0 {}
+L 4 10 -20 10 20 {dash=3}
+B 5 17.5 -32.5 22.5 -27.5 {name=d dir=inout}
+B 5 -22.5 -2.5 -17.5 2.5 {name=g dir=in}
+B 5 17.5 27.5 22.5 32.5 {name=s dir=inout}
+B 5 17.5 -2.5 22.5 2.5 {name=b dir=in}
+T {@w\\/@l\\/@m} 12.5 -18.75 0 0 0.2 0.2 {}
+T {@spiceprefix@name} 12.5 7.5 0 0 0.2 0.2 {}
+T {D} 25 -27.5 0 0 0.15 0.15 {}
+T {@#0:net_name} 25 -42.5 0 0 0.15 0.15 {layer=15}
+T {@#2:net_name} 25 32.5 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} -25 -12.5 0 1 0.15 0.15 {layer=15}
+T {@#3:net_name} 25 0.625 0 0 0.15 0.15 {layer=15}
diff --git a/xschem_library/logic/test_mos_verilog.sch b/xschem_library/logic/test_mos_verilog.sch
index e25971f3..16729329 100644
--- a/xschem_library/logic/test_mos_verilog.sch
+++ b/xschem_library/logic/test_mos_verilog.sch
@@ -4,18 +4,25 @@ K {}
 V {}
 S {}
 E {}
+P 4 6 1040 -360 950 -360 950 -370 930 -360 950 -350 950 -360 {}
 T {Set netlist mode to 'verilog netlist'
 (Options menu), then press 'Netlist'
 and 'Simulate' button.
 You need to have Icarus verilog installed
 Configure the verilog simulator in 
 Simulation-> Configure simulators and tools'
-menu.} 800 -240 0 0 0.4 0.4 {}
+menu.} 1050 -240 0 0 0.4 0.4 {}
 T {Trivial Depletion NMOS inverter simulation in verilog} 140 -670 0 0 0.7 0.7 {}
 T {NMOS
 depletion
 load} 420 -520 0 0 0.4 0.4 {}
 T {CMOS} 710 -520 0 0 0.4 0.4 {}
+T {NMOS
+Enhancement
+load } 980 -520 0 0 0.4 0.4 {}
+T {For Verilog simulations put nmos
+upside-down, drain is the output node.
+} 1050 -390 0 0 0.4 0.4 {}
 N 380 -480 380 -420 { lab=VDD}
 N 380 -390 440 -390 { lab=GND}
 N 380 -230 440 -230 { lab=GND}
@@ -33,6 +40,15 @@ N 550 -230 610 -230 { lab=IN}
 N 650 -310 720 -310 { lab=OUT2}
 N 650 -390 710 -390 { lab=VDD}
 N 610 -390 610 -230 { lab=IN}
+N 920 -480 920 -420 { lab=VDD}
+N 920 -230 980 -230 { lab=GND}
+N 920 -360 920 -260 { lab=OUT3}
+N 920 -200 920 -160 { lab=GND}
+N 820 -230 880 -230 { lab=IN}
+N 920 -310 990 -310 { lab=OUT3}
+N 920 -390 980 -390 { lab=GND}
+N 880 -440 880 -390 { lab=VDD}
+N 880 -440 920 -440 { lab=VDD}
 C {nmos4.sym} 360 -230 0 0 {name=M1 model=nmos w=5u l=0.18u m=1 del=10}
 C {nmos4_depl.sym} 360 -390 0 0 {name=M3 model=nmos w=5u l=0.18u m=1 del=10}
 C {gnd.sym} 440 -390 0 0 {name=l1 lab=GND}
@@ -67,3 +83,11 @@ C {lab_pin.sym} 720 -310 0 1 {name=l12 sig_type=std_logic lab=OUT2}
 C {pmos4.sym} 630 -390 0 0 {name=M4 model=pmos w=5u l=0.18u m=1}
 C {vdd.sym} 710 -390 0 0 {name=l13 lab=VDD value=1}
 C {noconn.sym} 300 -230 1 0 {name=l14}
+C {nmos4.sym} 900 -230 0 0 {name=M5 model=nmos w=5u l=0.18u m=1 del=10}
+C {gnd.sym} 980 -230 0 0 {name=l15 lab=GND}
+C {gnd.sym} 920 -160 0 0 {name=l16 lab=GND }
+C {vdd.sym} 920 -480 0 0 {name=l17 lab=VDD }
+C {lab_pin.sym} 820 -230 0 0 {name=l18 sig_type=std_logic lab=IN verilog_type=reg}
+C {lab_pin.sym} 990 -310 0 1 {name=l19 sig_type=std_logic lab=OUT3}
+C {gnd.sym} 980 -390 0 0 {name=l20 lab=GND}
+C {rnmos4.sym} 900 -390 2 1 {name=M6 model=nmos w=5u l=0.18u m=1 del=10}