From d4fe981525af6ffbcb3673892be8f276e036e0fe Mon Sep 17 00:00:00 2001 From: Stefan Frederik Date: Tue, 13 Sep 2022 12:01:58 +0200 Subject: [PATCH] ngspice_backannotate.tcl: handle Xyce operating point data, removed hspice_netlist (no more existent) --- src/flatten_savenodes.awk | 1 - src/ngspice_backannotate.tcl | 6 +- src/spice.awk | 110 +++++++++++---------------- src/tedax.awk | 8 -- src/xschem.tcl | 18 ++--- src/xschemrc | 1 - xschem_library/examples/poweramp.sch | 34 +++++---- 7 files changed, 71 insertions(+), 107 deletions(-) diff --git a/src/flatten_savenodes.awk b/src/flatten_savenodes.awk index ac78e401..9989ea53 100755 --- a/src/flatten_savenodes.awk +++ b/src/flatten_savenodes.awk @@ -33,7 +33,6 @@ BEGIN{ while( ARGV[1] ~ /^[-]/) { - if(ARGV[1] == "-hspice") hspice = 1 if(ARGV[1] == "-xyce") { xyce = 1} for(i=2; i<= ARGC;i++) { ARGV[i-1] = ARGV[i] diff --git a/src/ngspice_backannotate.tcl b/src/ngspice_backannotate.tcl index 077bf51f..ce8144aa 100644 --- a/src/ngspice_backannotate.tcl +++ b/src/ngspice_backannotate.tcl @@ -41,8 +41,10 @@ proc ngspice::read_ngspice_raw {arr fp} { set n_points [lindex $line end] } if {$variables} { - set var([lindex $line 1]) {} - set idx([lindex $line 0]) [lindex $line 1] + set nodename [string tolower [lindex $line 1]] + regsub -all {:} $nodename {.} nodename + set var($nodename) {} + set idx([lindex $line 0]) $nodename } if {[regexp {^Variables:} $line]} { set variables 1 diff --git a/src/spice.awk b/src/spice.awk index 10e72ede..c55f6740 100755 --- a/src/spice.awk +++ b/src/spice.awk @@ -28,7 +28,6 @@ BEGIN{ user_code=0 #20180129 while( (ARGV[1] ~ /^[-]/) || (ARGV[1] ~ /^$/) ) { - if(ARGV[1] == "-hspice") hspice = 1 if(ARGV[1] == "-xyce") { xyce = 1} for(i=2; i<= ARGC;i++) { ARGV[i-1] = ARGV[i] @@ -62,16 +61,6 @@ END{ ## resolve parametric instance name vector multiplicity substitute_instance_param() - if(xyce == 1) { - for(i=0; i v - sub(/^.*\(/,"", $i) - sub(/\).*/,"", $i) - num = split($i, name, ",") - for(j=1; j<= num; j++) { - print saveinstr " " saveanalysis attr savetype "(" name[j] ")" + if(!xyce) { + $1="" + $0 = $0 # reparse line for field splitting + + gsub(/ *\?-?[0-9]+ */, "") # in some cases ?-1 is printed (unknow multiplicity) + gsub(/\( */, "(") + gsub(/ *\)/, ")") + for(i=1; i<=NF; i++) { + savetype=$i; sub(/\(.*/,"", savetype) # v(...) --> v + sub(/^.*\(/,"", $i) + sub(/\).*/,"", $i) + num = split($i, name, ",") + for(j=1; j<= num; j++) { + print saveinstr " " savetype "(" name[j] ")" + } } } diff --git a/src/tedax.awk b/src/tedax.awk index 2de7c154..3c824ae4 100755 --- a/src/tedax.awk +++ b/src/tedax.awk @@ -23,14 +23,6 @@ BEGIN{ -## handle options -# if( ARGV[1] == "-hspice" ) { -# hspice=1 -# for(i=2; i<= ARGC;i++) { -# ARGV[i-1] = ARGV[i] -# } -# ARGC-- -# } } ##1 2 3 4 5 6 diff --git a/src/xschem.tcl b/src/xschem.tcl index 436b61aa..bd7ba5a2 100644 --- a/src/xschem.tcl +++ b/src/xschem.tcl @@ -360,7 +360,7 @@ proc ev {s} { } } proc netlist {source_file show netlist_file} { - global XSCHEM_SHAREDIR flat_netlist hspice_netlist netlist_dir + global XSCHEM_SHAREDIR flat_netlist netlist_dir global verilog_2001 debug_var OS verilog_bitblast simuldir @@ -368,11 +368,6 @@ proc netlist {source_file show netlist_file} { if {$debug_var <= -1} { puts "netlist: source_file=$source_file, netlist_type=$netlist_type" } set dest $netlist_dir/$netlist_file if {$netlist_type eq {spice}} { - if { $hspice_netlist == 1 } { - set simulator {-hspice} - } else { - set simulator {} - } if { [sim_is_xyce] } { set xyce {-xyce} } else { @@ -382,9 +377,9 @@ proc netlist {source_file show netlist_file} { set brk ${XSCHEM_SHAREDIR}/break.awk set flatten ${XSCHEM_SHAREDIR}/flatten.awk if {$flat_netlist==0} { - eval exec {awk -f $cmd -- $simulator $xyce $source_file | awk -f $brk > $dest} + eval exec {awk -f $cmd -- $xyce $source_file | awk -f $brk > $dest} } else { - eval exec {awk -f $cmd -- $simulator $xyce $source_file | awk -f $flatten | awk -f $brk > $dest} + eval exec {awk -f $cmd -- $xyce $source_file | awk -f $flatten | awk -f $brk > $dest} } if ![string compare $show "show"] { textwindow $dest @@ -4650,7 +4645,7 @@ set tctx::global_list { graph_bus graph_digital graph_logx graph_logy graph_sel_color graph_schname graph_selected graph_sel_wave graph_sort graph_unlocked - hide_empty_graphs hide_symbols hsize hspice_netlist + hide_empty_graphs hide_symbols hsize incr_hilight infowindow_text INITIALINSTDIR INITIALLOADDIR INITIALPROPDIR INITIALTEXTDIR input_line_cmd input_line_data launcher_default_program light_colors line_width local_netlist_dir measure_text @@ -4896,7 +4891,7 @@ proc switch_undo {} { proc build_widgets { {topwin {} } } { global XSCHEM_SHAREDIR tabbed_interface simulate_bg global colors recentfile color_ps transparent_svg menu_debug_var enable_stretch - global netlist_show flat_netlist split_files hspice_netlist tmp_bus_char + global netlist_show flat_netlist split_files tmp_bus_char global draw_grid big_grid_points sym_txt change_lw incr_hilight symbol_width global cadgrid draw_window show_pin_net_names toolbar_visible hide_symbols undo_type global disable_unique_names persistent_command autotrim_wires en_hilight_conn_inst @@ -5037,8 +5032,6 @@ proc build_widgets { {topwin {} } } { } $topwin.menubar.option.menu add checkbutton -label "Split netlist" -variable split_files \ -accelerator {} - $topwin.menubar.option.menu add checkbutton -label "hspice / ngspice netlist" -variable hspice_netlist \ - -accelerator {} $topwin.menubar.option.menu add command -label "Replace \[ and \] for buses in SPICE netlist" \ -command { input_line "Enter two characters to replace default bus \[\] delimiters:" "set tmp_bus_char" @@ -5642,7 +5635,6 @@ set_ne netlist_dir "$USER_CONF_DIR/simulations" set_ne netlist_type spice set_ne local_netlist_dir 0 ;# if set use /simulation for netlist and sims set_ne bus_replacement_char {} ;# use {<>} to replace [] with <> in bussed signals -set_ne hspice_netlist 1 set_ne top_subckt 0 set_ne hide_empty_graphs 0 ;# if set to 1 waveform boxes will be hidden if no raw file loaded set_ne spiceprefix 1 diff --git a/src/xschemrc b/src/xschemrc index 85045be0..f089a5e3 100644 --- a/src/xschemrc +++ b/src/xschemrc @@ -123,7 +123,6 @@ # set netlist_type spice #### Some netlisting options (these are the defaults) -# set hspice_netlist 1 # set verilog_2001 1 #### to use a fixed line with set change_lw to 0 and set some value to line_width diff --git a/xschem_library/examples/poweramp.sch b/xschem_library/examples/poweramp.sch index 943a9475..b9be7ca7 100644 --- a/xschem_library/examples/poweramp.sch +++ b/xschem_library/examples/poweramp.sch @@ -19,8 +19,8 @@ B 2 1200 -500 1880 -310 {flags=graph y1 = -0.0059 y2 = 11 divy = 6 -x1=0.0457674 -x2=0.0462507 +x1=0.024209 +x2=0.0246776 divx=10 node="i(v.x1.vu) i(v.x0.vu) @@ -32,8 +32,8 @@ B 2 1200 -830 1880 -520 {flags=graph y1 = -49 y2 = 59 divy = 12 -x1=0.0457674 -x2=0.0462507 +x1=0.024209 +x2=0.0246776 divx=10 node="outp outm @@ -47,8 +47,8 @@ B 2 1200 -1020 1880 -830 {flags=graph y1 = 2.4e-11 y2 = 840 divy = 6 -x1=0.0457674 -x2=0.0462507 +x1=0.024209 +x2=0.0246776 divx=10 @@ -60,8 +60,8 @@ B 2 1200 -310 1880 -120 {flags=graph y1 = 0.0077 y2 = 850 divy = 6 -x1=0.0457674 -x2=0.0462507 +x1=0.024209 +x2=0.0246776 divx=10 @@ -210,9 +210,9 @@ C {lab_pin.sym} 700 -1120 0 1 {name=p23 lab=REFM} C {lab_pin.sym} 240 -250 0 0 {name=p8 lab=INX} C {lab_pin.sym} 870 -1050 0 0 {name=p126 lab=VSS} C {lab_pin.sym} 950 -1200 0 1 {name=p127 lab=IN} -C {capa.sym} 550 -800 0 0 {name=C5 m=1 value="100n ic=0"} +C {capa.sym} 550 -800 0 0 {name=C5 m=1 value="100n ; ic=0"} C {lab_pin.sym} 550 -290 0 0 {name=p11 lab=VSS} -C {capa.sym} 550 -340 0 0 {name=C6 m=1 value="100n ic=0"} +C {capa.sym} 550 -340 0 0 {name=C6 m=1 value="100n ; ic=0"} C {lab_pin.sym} 350 -200 0 0 {name=p28 lab=VSS} C {lab_pin.sym} 350 -660 0 0 {name=p1 lab=VSS} C {res.sym} 550 -460 0 1 {name=R2 m=1 value='100k'} @@ -226,9 +226,9 @@ C {lab_pin.sym} 240 -860 0 0 {name=p18 lab=VPP} C {res.sym} 260 -620 0 1 {name=R5 m=1 value=100k} C {lab_pin.sym} 260 -570 0 0 {name=p10 lab=VSS} C {res.sym} 400 -950 0 1 {name=R8 m=1 value=100k} -C {capa.sym} 170 -220 1 0 {name=C4 m=1 value="100n ic=0"} +C {capa.sym} 170 -220 1 0 {name=C4 m=1 value="100n ; ic=0"} C {lab_pin.sym} 140 -220 0 0 {name=p0 lab=IN} -C {capa.sym} 150 -680 1 0 {name=C1 m=1 value="100n ic=0"} +C {capa.sym} 150 -680 1 0 {name=C1 m=1 value="100n ; ic=0"} C {lab_pin.sym} 120 -680 0 0 {name=p17 lab=VSS} C {lab_pin.sym} 240 -710 0 0 {name=p22 lab=VSSX} C {res.sym} 920 -1200 1 1 {name=R10 m=1 value=2} @@ -313,8 +313,7 @@ C {spice_probe.sym} 660 -1200 0 0 {name=p42 analysis=tran voltage=0.0000e+00} C {spice_probe.sym} 670 -1120 0 0 {name=p43 analysis=tran voltage=0.0000e+00} C {spice_probe.sym} 950 -1200 0 0 {name=p44 analysis=tran voltage=0.0000e+00} C {launcher.sym} 1000 -270 0 0 {name=h1 -descr="Backannotate -(ngspice)" +descr="Backannotate" tclcommand="ngspice::annotate $netlist_dir/poweramp_op.raw"} C {ngspice_get_expr.sym} 130 -1010 0 0 {name=r19 node="[ngspice::get_current \{r9[i]\}]" @@ -374,10 +373,12 @@ vvss vss 0 dc 0 ** SPICE models for active devices and put them into the below ** referenced file in simulation directory. .include \\"models_poweramp.txt\\" -* .op .tran 8e-7 0.07 uic +* .op .print tran format=raw file=poweramp_xyce.raw v(*) i(*) + v(x1:*) v(x0:*) i(x1:*) i(x0:*) +* .print dc format=raw file=poweramp_op.raw v(*) i(*) v(x1:*) v(x0:*) i(x1:*) i(x0:*) + "} C {launcher.sym} 1495 -1165 0 0 {name=h7 descr="load Xyce waves" @@ -385,3 +386,6 @@ tclcommand=" xschem raw_read $netlist_dir/poweramp_xyce.raw " } +C {ngspice_probe.sym} 880 -1200 0 1 {name=p29} +C {ngspice_probe.sym} 550 -830 0 1 {name=p29} +C {ngspice_probe.sym} 550 -750 0 1 {name=p29}