From cd7eb3ab54ca542e006df101898c831e596bea16 Mon Sep 17 00:00:00 2001 From: Stefan Frederik Date: Fri, 24 Jun 2022 00:36:12 +0200 Subject: [PATCH] update license info --- doc/xschem_man/developer_info.html | 2 +- doc/xschem_man/xschem_footer.html | 2 +- src/actions.c | 4 ++-- src/break.awk | 2 +- src/callback.c | 2 +- src/check.c | 2 +- src/clip.c | 2 +- src/convert_to_verilog2001.awk | 2 +- src/draw.c | 2 +- src/editprop.c | 2 +- src/expandlabel.y | 2 +- src/findnet.c | 2 +- src/flatten.awk | 2 +- src/flatten_savenodes.awk | 2 +- src/font.c | 2 +- src/globals.c | 2 +- src/gschemtoxschem.awk | 2 +- src/hash_iterator.c | 2 +- src/hilight.c | 2 +- src/hspice_backannotate.tcl | 2 +- src/icon.c | 2 +- src/in_memory_undo.c | 2 +- src/main.c | 2 +- src/make_sym.awk | 2 +- src/make_sym_lcc.awk | 2 +- src/move.c | 2 +- src/netlist.c | 2 +- src/ngspice_backannotate.tcl | 2 +- src/node_hash.c | 2 +- src/options.c | 2 +- src/parselabel.l | 2 +- src/paste.c | 2 +- src/psprint.c | 2 +- src/rawtovcd.c | 2 +- src/resources.tcl | 2 +- src/save.c | 2 +- src/scheduler.c | 2 +- src/select.c | 2 +- src/spice.awk | 2 +- src/spice_netlist.c | 2 +- src/store.c | 2 +- src/svgdraw.c | 2 +- src/symgen.awk | 2 +- src/tedax.awk | 2 +- src/tedax_netlist.c | 2 +- src/token.c | 2 +- src/verilog.awk | 2 +- src/verilog_netlist.c | 2 +- src/vhdl.awk | 2 +- src/vhdl_netlist.c | 2 +- src/xinit.c | 2 +- src/xschem.h | 2 +- src/xschem.tcl | 4 ++-- tests/create_save.tcl | 2 +- tests/netlisting.tcl | 2 +- tests/open_close.tcl | 2 +- tests/run_regression.tcl | 2 +- tests/test_utility.tcl | 2 +- 58 files changed, 60 insertions(+), 60 deletions(-) diff --git a/doc/xschem_man/developer_info.html b/doc/xschem_man/developer_info.html index a511f162..2f94f7fb 100644 --- a/doc/xschem_man/developer_info.html +++ b/doc/xschem_man/developer_info.html @@ -196,7 +196,7 @@ v {xschem version=2.9.7 file_version=1.2} 

 v {xschem version=3.0.0 file_version=1.2 
-* Copyright 2021 Stefan Frederik Schippers
+* Copyright 2022 Stefan Frederik Schippers
 * 
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
diff --git a/doc/xschem_man/xschem_footer.html b/doc/xschem_man/xschem_footer.html
index 0c887e23..47960e7a 100644
--- a/doc/xschem_man/xschem_footer.html
+++ b/doc/xschem_man/xschem_footer.html
@@ -20,7 +20,7 @@
         top: 12px;
         right: 30px;
         float: right;">
-        Copyright(C) 1998 - 2021 Stefan Schippers
+        Copyright(C) 1998 - 2022 Stefan Schippers
      

 
 
diff --git a/src/actions.c b/src/actions.c
index e3a01a98..ff79411c 100644
--- a/src/actions.c
+++ b/src/actions.c
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -104,7 +104,7 @@ void set_modify(int mod)
 void print_version()
 {
   printf("XSCHEM V%s\n", XSCHEM_VERSION);
-  printf("Copyright 1998-2021 Stefan Schippers\n");
+  printf("Copyright 1998-2022 Stefan Schippers\n");
   printf("\n");
   printf("This is free software; see the source for copying conditions.  There is NO\n");
   printf("warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n");
diff --git a/src/break.awk b/src/break.awk
index c63ff510..1b114cd2 100755
--- a/src/break.awk
+++ b/src/break.awk
@@ -5,7 +5,7 @@
 #  This file is part of XSCHEM,
 #  a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit 
 #  simulation.
-#  Copyright (C) 1998-2021 Stefan Frederik Schippers
+#  Copyright (C) 1998-2022 Stefan Frederik Schippers
 # 
 #  This program is free software; you can redistribute it and/or modify
 #  it under the terms of the GNU General Public License as published by
diff --git a/src/callback.c b/src/callback.c
index 5e1d343c..3282b53b 100644
--- a/src/callback.c
+++ b/src/callback.c
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/check.c b/src/check.c
index a8342e9d..1c51cea6 100644
--- a/src/check.c
+++ b/src/check.c
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/clip.c b/src/clip.c
index 7c830723..486ed097 100644
--- a/src/clip.c
+++ b/src/clip.c
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/convert_to_verilog2001.awk b/src/convert_to_verilog2001.awk
index d5b640ad..9d42a18c 100755
--- a/src/convert_to_verilog2001.awk
+++ b/src/convert_to_verilog2001.awk
@@ -5,7 +5,7 @@
 #  This file is part of XSCHEM,
 #  a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit 
 #  simulation.
-#  Copyright (C) 1998-2021 Stefan Frederik Schippers
+#  Copyright (C) 1998-2022 Stefan Frederik Schippers
 # 
 #  This program is free software; you can redistribute it and/or modify
 #  it under the terms of the GNU General Public License as published by
diff --git a/src/draw.c b/src/draw.c
index be235cab..dcff40ba 100644
--- a/src/draw.c
+++ b/src/draw.c
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/editprop.c b/src/editprop.c
index 3255baa2..f9cb14c7 100644
--- a/src/editprop.c
+++ b/src/editprop.c
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/expandlabel.y b/src/expandlabel.y
index a6bb4aae..8b8ca23e 100644
--- a/src/expandlabel.y
+++ b/src/expandlabel.y
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit 
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/findnet.c b/src/findnet.c
index 8232b0ea..2ac5dbf9 100644
--- a/src/findnet.c
+++ b/src/findnet.c
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/flatten.awk b/src/flatten.awk
index 8ddb87fa..746d3deb 100755
--- a/src/flatten.awk
+++ b/src/flatten.awk
@@ -5,7 +5,7 @@
 #  This file is part of XSCHEM,
 #  a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit 
 #  simulation.
-#  Copyright (C) 1998-2021 Stefan Frederik Schippers
+#  Copyright (C) 1998-2022 Stefan Frederik Schippers
 # 
 #  This program is free software; you can redistribute it and/or modify
 #  it under the terms of the GNU General Public License as published by
diff --git a/src/flatten_savenodes.awk b/src/flatten_savenodes.awk
index 7824dfba..ac78e401 100755
--- a/src/flatten_savenodes.awk
+++ b/src/flatten_savenodes.awk
@@ -5,7 +5,7 @@
 #  This file is part of XSCHEM,
 #  a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit 
 #  simulation.
-#  Copyright (C) 1998-2021 Stefan Frederik Schippers
+#  Copyright (C) 1998-2022 Stefan Frederik Schippers
 # 
 #  This program is free software; you can redistribute it and/or modify
 #  it under the terms of the GNU General Public License as published by
diff --git a/src/font.c b/src/font.c
index 851c67c6..2ad8a506 100644
--- a/src/font.c
+++ b/src/font.c
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/globals.c b/src/globals.c
index b5bc7566..220907cc 100644
--- a/src/globals.c
+++ b/src/globals.c
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/gschemtoxschem.awk b/src/gschemtoxschem.awk
index 38f90953..2e685379 100755
--- a/src/gschemtoxschem.awk
+++ b/src/gschemtoxschem.awk
@@ -5,7 +5,7 @@
 #  This file is part of XSCHEM,
 #  a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit 
 #  simulation.
-#  Copyright (C) 1998-2021 Stefan Frederik Schippers
+#  Copyright (C) 1998-2022 Stefan Frederik Schippers
 # 
 #  This program is free software; you can redistribute it and/or modify
 #  it under the terms of the GNU General Public License as published by
diff --git a/src/hash_iterator.c b/src/hash_iterator.c
index aec59779..62fddd72 100644
--- a/src/hash_iterator.c
+++ b/src/hash_iterator.c
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/hilight.c b/src/hilight.c
index 766d86d8..44054c0b 100644
--- a/src/hilight.c
+++ b/src/hilight.c
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/hspice_backannotate.tcl b/src/hspice_backannotate.tcl
index a39058d8..1154cac2 100644
--- a/src/hspice_backannotate.tcl
+++ b/src/hspice_backannotate.tcl
@@ -4,7 +4,7 @@
 #  This file is part of XSCHEM,
 #  a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit 
 #  simulation.
-#  Copyright (C) 1998-2021 Stefan Frederik Schippers
+#  Copyright (C) 1998-2022 Stefan Frederik Schippers
 # 
 #  This program is free software; you can redistribute it and/or modify
 #  it under the terms of the GNU General Public License as published by
diff --git a/src/icon.c b/src/icon.c
index 10191eee..851881f5 100644
--- a/src/icon.c
+++ b/src/icon.c
@@ -4,7 +4,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/in_memory_undo.c b/src/in_memory_undo.c
index 408ca983..1ee1a377 100644
--- a/src/in_memory_undo.c
+++ b/src/in_memory_undo.c
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/main.c b/src/main.c
index 006082ea..996659bc 100644
--- a/src/main.c
+++ b/src/main.c
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/make_sym.awk b/src/make_sym.awk
index 98631919..b2d7544c 100755
--- a/src/make_sym.awk
+++ b/src/make_sym.awk
@@ -5,7 +5,7 @@
 #  This file is part of XSCHEM,
 #  a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit 
 #  simulation.
-#  Copyright (C) 1998-2021 Stefan Frederik Schippers
+#  Copyright (C) 1998-2022 Stefan Frederik Schippers
 # 
 #  This program is free software; you can redistribute it and/or modify
 #  it under the terms of the GNU General Public License as published by
diff --git a/src/make_sym_lcc.awk b/src/make_sym_lcc.awk
index e62a0c4c..3f234d61 100644
--- a/src/make_sym_lcc.awk
+++ b/src/make_sym_lcc.awk
@@ -5,7 +5,7 @@
 #  This file is part of XSCHEM,
 #  a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit 
 #  simulation.
-#  Copyright (C) 1998-2021 Stefan Frederik Schippers
+#  Copyright (C) 1998-2022 Stefan Frederik Schippers
 # 
 #  This program is free software; you can redistribute it and/or modify
 #  it under the terms of the GNU General Public License as published by
diff --git a/src/move.c b/src/move.c
index 9a2075de..581cad88 100644
--- a/src/move.c
+++ b/src/move.c
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/netlist.c b/src/netlist.c
index 99e4303d..5297f529 100644
--- a/src/netlist.c
+++ b/src/netlist.c
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/ngspice_backannotate.tcl b/src/ngspice_backannotate.tcl
index cd767c7f..1b3cfe6f 100644
--- a/src/ngspice_backannotate.tcl
+++ b/src/ngspice_backannotate.tcl
@@ -4,7 +4,7 @@
 #  This file is part of XSCHEM,
 #  a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit 
 #  simulation.
-#  Copyright (C) 1998-2021 Stefan Frederik Schippers
+#  Copyright (C) 1998-2022 Stefan Frederik Schippers
 # 
 #  This program is free software; you can redistribute it and/or modify
 #  it under the terms of the GNU General Public License as published by
diff --git a/src/node_hash.c b/src/node_hash.c
index 55d2dc76..3ac58a39 100644
--- a/src/node_hash.c
+++ b/src/node_hash.c
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/options.c b/src/options.c
index a381012c..d7a457d7 100644
--- a/src/options.c
+++ b/src/options.c
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/parselabel.l b/src/parselabel.l
index 4b4ec382..32b70af8 100644
--- a/src/parselabel.l
+++ b/src/parselabel.l
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit 
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/paste.c b/src/paste.c
index 4ce2b0be..29ae0ec7 100644
--- a/src/paste.c
+++ b/src/paste.c
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/psprint.c b/src/psprint.c
index 5b0d94eb..2bca3307 100644
--- a/src/psprint.c
+++ b/src/psprint.c
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/rawtovcd.c b/src/rawtovcd.c
index f0640f81..78177327 100644
--- a/src/rawtovcd.c
+++ b/src/rawtovcd.c
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/resources.tcl b/src/resources.tcl
index e459f492..81f6e925 100644
--- a/src/resources.tcl
+++ b/src/resources.tcl
@@ -4,7 +4,7 @@
 #  This file is part of XSCHEM,
 #  a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit 
 #  simulation.
-#  Copyright (C) 1998-2021 Stefan Frederik Schippers
+#  Copyright (C) 1998-2022 Stefan Frederik Schippers
 # 
 #  This program is free software; you can redistribute it and/or modify
 #  it under the terms of the GNU General Public License as published by
diff --git a/src/save.c b/src/save.c
index a142fdb9..a2005703 100644
--- a/src/save.c
+++ b/src/save.c
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/scheduler.c b/src/scheduler.c
index b0837d5e..c1dd52ed 100644
--- a/src/scheduler.c
+++ b/src/scheduler.c
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/select.c b/src/select.c
index eb9f4f0a..fda05752 100644
--- a/src/select.c
+++ b/src/select.c
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/spice.awk b/src/spice.awk
index e9e4160b..257e3caa 100755
--- a/src/spice.awk
+++ b/src/spice.awk
@@ -5,7 +5,7 @@
 #  This file is part of XSCHEM,
 #  a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit 
 #  simulation.
-#  Copyright (C) 1998-2021 Stefan Frederik Schippers
+#  Copyright (C) 1998-2022 Stefan Frederik Schippers
 # 
 #  This program is free software; you can redistribute it and/or modify
 #  it under the terms of the GNU General Public License as published by
diff --git a/src/spice_netlist.c b/src/spice_netlist.c
index 2c20f42d..8d759737 100644
--- a/src/spice_netlist.c
+++ b/src/spice_netlist.c
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/store.c b/src/store.c
index acd1a593..b27d8d93 100644
--- a/src/store.c
+++ b/src/store.c
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/svgdraw.c b/src/svgdraw.c
index 673aab89..45b991af 100644
--- a/src/svgdraw.c
+++ b/src/svgdraw.c
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/symgen.awk b/src/symgen.awk
index f55ed355..036f1507 100755
--- a/src/symgen.awk
+++ b/src/symgen.awk
@@ -5,7 +5,7 @@
 #  This file is part of XSCHEM,
 #  a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit 
 #  simulation.
-#  Copyright (C) 1998-2021 Stefan Frederik Schippers
+#  Copyright (C) 1998-2022 Stefan Frederik Schippers
 # 
 #  This program is free software; you can redistribute it and/or modify
 #  it under the terms of the GNU General Public License as published by
diff --git a/src/tedax.awk b/src/tedax.awk
index 4b8d9b64..2de7c154 100755
--- a/src/tedax.awk
+++ b/src/tedax.awk
@@ -5,7 +5,7 @@
 #  This file is part of XSCHEM,
 #  a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit 
 #  simulation.
-#  Copyright (C) 1998-2021 Stefan Frederik Schippers
+#  Copyright (C) 1998-2022 Stefan Frederik Schippers
 # 
 #  This program is free software; you can redistribute it and/or modify
 #  it under the terms of the GNU General Public License as published by
diff --git a/src/tedax_netlist.c b/src/tedax_netlist.c
index 454fe368..6d26c8dd 100644
--- a/src/tedax_netlist.c
+++ b/src/tedax_netlist.c
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/token.c b/src/token.c
index ea1bd543..6a5f7259 100644
--- a/src/token.c
+++ b/src/token.c
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/verilog.awk b/src/verilog.awk
index a25d3757..51277d50 100755
--- a/src/verilog.awk
+++ b/src/verilog.awk
@@ -5,7 +5,7 @@
 #  This file is part of XSCHEM,
 #  a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit 
 #  simulation.
-#  Copyright (C) 1998-2021 Stefan Frederik Schippers
+#  Copyright (C) 1998-2022 Stefan Frederik Schippers
 # 
 #  This program is free software; you can redistribute it and/or modify
 #  it under the terms of the GNU General Public License as published by
diff --git a/src/verilog_netlist.c b/src/verilog_netlist.c
index 336e0f43..8cb90f81 100644
--- a/src/verilog_netlist.c
+++ b/src/verilog_netlist.c
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/vhdl.awk b/src/vhdl.awk
index 3bbd2e37..2a5a9d9e 100755
--- a/src/vhdl.awk
+++ b/src/vhdl.awk
@@ -5,7 +5,7 @@
 #  This file is part of XSCHEM,
 #  a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit 
 #  simulation.
-#  Copyright (C) 1998-2021 Stefan Frederik Schippers
+#  Copyright (C) 1998-2022 Stefan Frederik Schippers
 # 
 #  This program is free software; you can redistribute it and/or modify
 #  it under the terms of the GNU General Public License as published by
diff --git a/src/vhdl_netlist.c b/src/vhdl_netlist.c
index 94878238..fbe9fa81 100644
--- a/src/vhdl_netlist.c
+++ b/src/vhdl_netlist.c
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/xinit.c b/src/xinit.c
index 39de1267..ee67e1d1 100644
--- a/src/xinit.c
+++ b/src/xinit.c
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/xschem.h b/src/xschem.h
index 0f5cebad..d10387bb 100644
--- a/src/xschem.h
+++ b/src/xschem.h
@@ -3,7 +3,7 @@
  * This file is part of XSCHEM,
  * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
  * simulation.
- * Copyright (C) 1998-2021 Stefan Frederik Schippers
+ * Copyright (C) 1998-2022 Stefan Frederik Schippers
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/xschem.tcl b/src/xschem.tcl
index afd79764..9d5e458e 100644
--- a/src/xschem.tcl
+++ b/src/xschem.tcl
@@ -4,7 +4,7 @@
 #  This file is part of XSCHEM,
 #  a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit 
 #  simulation.
-#  Copyright (C) 1998-2021 Stefan Frederik Schippers
+#  Copyright (C) 1998-2022 Stefan Frederik Schippers
 # 
 #  This program is free software; you can redistribute it and/or modify
 #  it under the terms of the GNU General Public License as published by
@@ -2894,7 +2894,7 @@ proc about {} {
   button .about.link -text {http://repo.hu/projects/xschem} -font Underline-Font -fg blue -relief flat
   button .about.link2 -text {https://github.com/StefanSchippers/xschem} -font Underline-Font -fg blue -relief flat
   button .about.link3 -text {Online XSCHEM Manual} -font Underline-Font -fg blue -relief flat
-  label .about.copyright -text "\n Copyright 1998-2021 Stefan Schippers (stefan.schippers@gmail.com) \n
+  label .about.copyright -text "\n Copyright 1998-2022 Stefan Schippers (stefan.schippers@gmail.com) \n
  This is free software; see the source for copying conditions.  There is NO warranty;
  not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE\n"
   button .about.close -text Close -command {destroy .about} -font {Sans 18}
diff --git a/tests/create_save.tcl b/tests/create_save.tcl
index 160a6726..ac3df64c 100644
--- a/tests/create_save.tcl
+++ b/tests/create_save.tcl
@@ -4,7 +4,7 @@
 #  This file is part of XSCHEM,
 #  a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit 
 #  simulation.
-#  Copyright (C) 1998-2021 Stefan Frederik Schippers
+#  Copyright (C) 1998-2022 Stefan Frederik Schippers
 # 
 #  This program is free software; you can redistribute it and/or modify
 #  it under the terms of the GNU General Public License as published by
diff --git a/tests/netlisting.tcl b/tests/netlisting.tcl
index 6c18d3c3..a832333a 100644
--- a/tests/netlisting.tcl
+++ b/tests/netlisting.tcl
@@ -4,7 +4,7 @@
 #  This file is part of XSCHEM,
 #  a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit 
 #  simulation.
-#  Copyright (C) 1998-2021 Stefan Frederik Schippers
+#  Copyright (C) 1998-2022 Stefan Frederik Schippers
 # 
 #  This program is free software; you can redistribute it and/or modify
 #  it under the terms of the GNU General Public License as published by
diff --git a/tests/open_close.tcl b/tests/open_close.tcl
index 8dbcfdae..c03e21f2 100644
--- a/tests/open_close.tcl
+++ b/tests/open_close.tcl
@@ -4,7 +4,7 @@
 #  This file is part of XSCHEM,
 #  a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit 
 #  simulation.
-#  Copyright (C) 1998-2021 Stefan Frederik Schippers
+#  Copyright (C) 1998-2022 Stefan Frederik Schippers
 # 
 #  This program is free software; you can redistribute it and/or modify
 #  it under the terms of the GNU General Public License as published by
diff --git a/tests/run_regression.tcl b/tests/run_regression.tcl
index bcbbe232..94f1ae38 100644
--- a/tests/run_regression.tcl
+++ b/tests/run_regression.tcl
@@ -4,7 +4,7 @@
 #  This file is part of XSCHEM,
 #  a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit 
 #  simulation.
-#  Copyright (C) 1998-2021 Stefan Frederik Schippers
+#  Copyright (C) 1998-2022 Stefan Frederik Schippers
 # 
 #  This program is free software; you can redistribute it and/or modify
 #  it under the terms of the GNU General Public License as published by
diff --git a/tests/test_utility.tcl b/tests/test_utility.tcl
index 6696769f..4cb9a9c9 100644
--- a/tests/test_utility.tcl
+++ b/tests/test_utility.tcl
@@ -4,7 +4,7 @@
 #  This file is part of XSCHEM,
 #  a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit 
 #  simulation.
-#  Copyright (C) 1998-2021 Stefan Frederik Schippers
+#  Copyright (C) 1998-2022 Stefan Frederik Schippers
 # 
 #  This program is free software; you can redistribute it and/or modify
 #  it under the terms of the GNU General Public License as published by