From cd6ef788411346df3cff57214f5a8bb84957526d Mon Sep 17 00:00:00 2001 From: stefan schippers Date: Mon, 24 Apr 2023 13:26:04 +0200 Subject: [PATCH] schematic generator netlisting seems to work. renamed is_symgen() -> is_generator() --- src/actions.c | 22 ++++-- src/save.c | 22 ++++-- src/scheduler.c | 2 +- src/spice_netlist.c | 1 + src/token.c | 8 +- src/xinit.c | 2 +- src/xschem.h | 2 +- xschem_library/generators/my_inv.sch | 27 +++++++ xschem_library/generators/my_inv.sym | 22 ++++++ xschem_library/generators/schematicgen | 81 ++++++++++++++++++++ xschem_library/generators/symbolgen | 36 ++++----- xschem_library/generators/test_symbolgen.sch | 45 ++++++++--- 12 files changed, 222 insertions(+), 48 deletions(-) create mode 100644 xschem_library/generators/my_inv.sch create mode 100644 xschem_library/generators/my_inv.sym create mode 100755 xschem_library/generators/schematicgen diff --git a/src/actions.c b/src/actions.c index 48ac0b73..c731cb56 100644 --- a/src/actions.c +++ b/src/actions.c @@ -1341,8 +1341,17 @@ void get_additional_symbols(int what) my_strdup(_ALLOC_ID_, &vhdl_sym_def, get_tok_value(xctx->inst[i].prop_ptr,"vhdl_sym_def",0)); sch = get_tok_value(xctx->inst[i].prop_ptr,"schematic",0); if(xctx->tok_size) { /* token exists */ - const char *sym = add_ext(rel_sym_path(sch), ".sym"); int j; + char *sym = NULL; + + dbg(1, "get_additional_symbols(): inst=%d, sch=%s\n", i, sch); + if(is_generator(sch)) { + my_strdup2(_ALLOC_ID_, &sym, sch); + dbg(1, "get_additional_symbols(): generator\n"); + } else { + my_strdup2(_ALLOC_ID_, &sym, add_ext(rel_sym_path(sch), ".sym")); + } + found = int_hash_lookup(&sym_table, sym, 0, XLOOKUP); if(!found) { j = xctx->symbols; @@ -1352,7 +1361,7 @@ void get_additional_symbols(int what) copy_symbol(&xctx->sym[j], xctx->inst[i].ptr + xctx->sym); xctx->sym[j].base_name = (xctx->inst[i].ptr + xctx->sym)->name; my_strdup(_ALLOC_ID_, &xctx->sym[j].name, sym); - + my_free(_ALLOC_ID_, &sym); if(spice_sym_def) my_strdup(_ALLOC_ID_, &xctx->sym[j].prop_ptr, subst_token(xctx->sym[j].prop_ptr, "spice_sym_def", spice_sym_def)); @@ -1392,9 +1401,12 @@ void get_sch_from_sym(char *filename, xSymbol *sym, int inst) strstr(xctx->current_dirname, "https://") == xctx->current_dirname) { web_url = 1; } + dbg(1, "get_sch_from_sym(): symbol %s inst=%d\n", sym->name, inst); if(inst >= 0) my_strdup(_ALLOC_ID_, &str_tmp, get_tok_value(xctx->inst[inst].prop_ptr, "schematic", 2)); if(!str_tmp) my_strdup2(_ALLOC_ID_, &str_tmp, get_tok_value(sym->prop_ptr, "schematic", 2)); - if(str_tmp[0]) { + if(str_tmp[0] && is_generator(str_tmp)) { /* generator: return as is */ + my_strncpy(filename, str_tmp, PATH_MAX); + } else if(str_tmp[0]) { /* @symname in schematic attribute will be replaced with symbol name */ my_strdup(_ALLOC_ID_, &sch, str_replace(str_tmp, "@symname", skip_dir(sym->name), '\\')); dbg(1, "get_sch_from_sym(): sch=%s\n", sch); @@ -1405,7 +1417,8 @@ void get_sch_from_sym(char *filename, xSymbol *sym, int inst) else my_strncpy(filename, abs_sym_path(sch, ""), PATH_MAX); my_free(_ALLOC_ID_, &sch); } else { - if(tclgetboolvar("search_schematic")) { + if(is_generator(sym->name)) my_strncpy(filename, sym->name, PATH_MAX); + else if(tclgetboolvar("search_schematic")) { /* for schematics referenced from web symbols do not build absolute path */ if(web_url) my_strncpy(filename, add_ext(sym->name, ".sch"), PATH_MAX); else my_strncpy(filename, abs_sym_path(sym->name, ".sch"), PATH_MAX); @@ -1421,7 +1434,6 @@ void get_sch_from_sym(char *filename, xSymbol *sym, int inst) } } - /* if( strstr(xctx->current_dirname, "http://") == xctx->current_dirname || * strstr(xctx->current_dirname, "https://") == xctx->current_dirname) { */ diff --git a/src/save.c b/src/save.c index 36eb8929..bbdb72d7 100644 --- a/src/save.c +++ b/src/save.c @@ -1642,7 +1642,7 @@ static void save_inst(FILE *fd, int select_only) fprintf(fd, " %.16g %.16g %hd %hd ",inst[i].x0, inst[i].y0, inst[i].rot, inst[i].flip ); save_ascii_string(inst[i].prop_ptr,fd, 1); if(embedded_saved && !embedded_saved[inst[i].ptr]) { - if(is_symgen(inst[i].name)) { + if(is_generator(inst[i].name)) { embedded_saved[inst[i].ptr] = 1; xctx->sym[inst[i].ptr].flags |= EMBEDDED; dbg(1, "save_inst(): setting symbol %d to embedded\n", inst[i].ptr); @@ -2431,12 +2431,10 @@ void load_schematic(int load_symbols, const char *fname, int reset_undo, int ale if(reset_undo) xctx->prev_set_modify = -1; /* will force set_modify(0) to set window title */ else xctx->prev_set_modify = 0; /* will prevent set_modify(0) from setting window title */ if(fname && fname[0]) { - /* int generator = 0; - tclvareval("is_xschem_file {", fname, "}", NULL); - if(!strcmp(tclresult(), "GENERATOR")) generator = 1; - */ + if(is_generator(fname) && !strstr(fname, ".xschem_embedded_")) generator = 1; my_strncpy(name, fname, S(name)); + /* remote web object specified */ if(strstr(fname , "http://") == fname || strstr(fname , "https://") == fname) { @@ -2488,7 +2486,16 @@ void load_schematic(int load_symbols, const char *fname, int reset_undo, int ale xctx->time_last_modify = 0; /* file does not exist, set mtime to 0 (undefined)*/ } } - if( (fd=fopen(name,fopen_read_mode))== NULL) { + if(generator) { + char *cmd; + cmd = get_generator_command(fname); + if(cmd) { + fd = popen(cmd, "r"); + my_free(_ALLOC_ID_, &cmd); + } else fd = NULL; + } + else fd=fopen(name,fopen_read_mode); + if( fd == NULL) { if(alert) { fprintf(errfp, "load_schematic(): unable to open file: %s, fname=%s\n", name, fname ); my_snprintf(msg, S(msg), "update; alert_ {Unable to open file: %s}", fname); @@ -2500,7 +2507,8 @@ void load_schematic(int load_symbols, const char *fname, int reset_undo, int ale clear_drawing(); dbg(1, "load_schematic(): reading file: %s\n", name); read_xschem_file(fd); - fclose(fd); /* 20150326 moved before load symbols */ + if(generator) pclose(fd); + else fclose(fd); /* 20150326 moved before load symbols */ if(reset_undo) set_modify(0); dbg(2, "load_schematic(): loaded file:wire=%d inst=%d\n",xctx->wires , xctx->instances); if(load_symbols) link_symbols_to_instances(-1); diff --git a/src/scheduler.c b/src/scheduler.c index ff6842ef..dad1db16 100644 --- a/src/scheduler.c +++ b/src/scheduler.c @@ -1791,7 +1791,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg { char s[30]; if(argc > 2) { - my_snprintf(s, S(s), "%d", is_symgen(argv[2])); + my_snprintf(s, S(s), "%d", is_generator(argv[2])); Tcl_SetResult(interp, s, TCL_VOLATILE); } } diff --git a/src/spice_netlist.c b/src/spice_netlist.c index 461a2cc8..306f7e2b 100644 --- a/src/spice_netlist.c +++ b/src/spice_netlist.c @@ -414,6 +414,7 @@ int global_spice_netlist(int global) /* netlister driver */ my_strncpy(xctx->current_dirname, tclresult(), S(xctx->current_dirname)); /* xctx->sym can be SCH or SYM, use hash to avoid writing duplicate subckt */ my_strdup(_ALLOC_ID_, &subckt_name, get_cell(xctx->sym[i].name, 0)); + dbg(1, "global_spice_netlist(): subckt_name=%s\n", subckt_name); if (str_hash_lookup(&subckt_table, subckt_name, "", XLOOKUP)==NULL) { str_hash_lookup(&subckt_table, subckt_name, "", XINSERT); diff --git a/src/token.c b/src/token.c index dfca4a9e..f2ab0a54 100644 --- a/src/token.c +++ b/src/token.c @@ -161,7 +161,7 @@ void check_unique_names(int rename) int_hash_free(&xctx->inst_table); } -int is_symgen(const char *name) +int is_generator(const char *name) { #ifdef __unix__ int res = 0; @@ -179,7 +179,7 @@ int is_symgen(const char *name) regcomp(re, "^[^ \t()]+\\([^()]*\\)[ \t]*$", REG_NOSUB | REG_EXTENDED); } if(!regexec(re, name, 0 , NULL, 0) ) res = 1; - dbg(1, "is_symgen(%s)=%d\n", name, res); + dbg(1, "is_generator(%s)=%d\n", name, res); /* regfree(&re); */ return res; #else @@ -226,7 +226,7 @@ char *get_generator_command(const char *str) my_strcat(_ALLOC_ID_, &gen_cmd, spc_idx); dbg(1, "get_generator_command(): cmd_filename=%s\n", cmd_filename); dbg(1, "get_generator_command(): gen_cmd=%s\n", gen_cmd); - dbg(1, "get_generator_command(): is_symgen=%d\n", is_symgen(str)); + dbg(1, "get_generator_command(): is_symgen=%d\n", is_generator(str)); end: my_free(_ALLOC_ID_, &cmd); @@ -238,7 +238,7 @@ int match_symbol(const char *name) /* never returns -1, if symbol not found loa int i,found, is_sym_generator; found=0; - is_sym_generator = is_symgen(name); + is_sym_generator = is_generator(name); for(i=0;isymbols; ++i) { /* dbg(1, "match_symbol(): name=%s, sym[i].name=%s\n",name, xctx->sym[i].name);*/ diff --git a/src/xinit.c b/src/xinit.c index 27222495..75849e9b 100644 --- a/src/xinit.c +++ b/src/xinit.c @@ -646,7 +646,7 @@ static void delete_schematic_data(int delete_pixmap) remove_symbols(); str_replace(NULL, NULL, NULL, 0); escape_chars(NULL); - is_symgen(NULL); + is_generator(NULL); free_rawfile(0); free_xschem_data(); /* delete the xctx struct */ } diff --git a/src/xschem.h b/src/xschem.h index 6783ba8d..adb01412 100644 --- a/src/xschem.h +++ b/src/xschem.h @@ -1482,7 +1482,7 @@ extern void hilight_parent_pins(void); extern void hilight_net_pin_mismatches(void); extern Node_hashentry **get_node_table_ptr(void); extern void change_elem_order(void); -extern int is_symgen(const char *name); +extern int is_generator(const char *name); extern char *str_chars_replace(const char *str, const char *replace_set, const char with); extern char *str_replace(const char *str, const char *rep, const char *with, int escape); extern char *escape_chars(const char *source); diff --git a/xschem_library/generators/my_inv.sch b/xschem_library/generators/my_inv.sch new file mode 100644 index 00000000..504c262e --- /dev/null +++ b/xschem_library/generators/my_inv.sch @@ -0,0 +1,27 @@ +v {xschem version=3.1.0 file_version=1.2 +} +G { +y <= not a after 0.1 ns ;} +K {} +V {assign #150 y=~a ;} +S {} +E {} +N 190 -250 190 -210 {lab=y} +N 190 -230 230 -230 {lab=y} +N 150 -280 150 -180 {lab=a} +N 110 -230 150 -230 {lab=a} +N 190 -280 270 -280 {lab=VCC} +N 270 -310 270 -280 {lab=VCC} +N 190 -310 270 -310 {lab=VCC} +N 190 -180 290 -180 {lab=0} +N 290 -180 290 -150 {lab=0} +N 190 -150 290 -150 {lab=0} +N 190 -350 190 -310 {lab=VCC} +N 190 -150 190 -130 {lab=0} +C {opin.sym} 230 -230 0 0 {name=p1 lab=y verilog_type=wire} +C {ipin.sym} 110 -230 0 0 {name=p2 lab=a} +C {p.sym} 170 -280 0 0 {name=m2 model=cmosp w=wp l=lp m=1 } +C {lab_pin.sym} 190 -350 0 0 {name=p149 lab=VCC} +C {lab_pin.sym} 190 -130 0 0 {name=p3 lab=0} +C {n.sym} 170 -180 0 0 {name=m1 model=cmosn w=wn l=lln m=1} +C {title.sym} 160 0 0 0 {name=l3 author="Stefan Schippers"} diff --git a/xschem_library/generators/my_inv.sym b/xschem_library/generators/my_inv.sym new file mode 100644 index 00000000..aaf3be29 --- /dev/null +++ b/xschem_library/generators/my_inv.sym @@ -0,0 +1,22 @@ +v {xschem version=3.1.0 file_version=1.2 +} +G {} +K {type=subcircuit +format="@name @pinlist @symname wn=@wn lln=@lln wp=@wp lp=@lp" +template="name=x1 wn=1u lln=2u wp=4u lp=2u" +} +V {} +S {} +E {} +L 4 -40 0 -20 0 {} +L 4 -20 -20 20 0 {} +L 4 -20 -20 -20 20 {} +L 4 -20 20 20 0 {} +L 4 30 -0 40 -0 {} +B 5 37.5 -2.5 42.5 2.5 {name=Y dir=out } +B 5 -42.5 -2.5 -37.5 2.5 {name=A dir=in } +A 4 25 -0 5 180 360 {} +T {@symname} -47.5 24 0 0 0.3 0.3 {} +T {@name} 25 -22 0 0 0.2 0.2 {} +T {Y} 7.5 -6.5 0 1 0.2 0.2 {} +T {A} -17.5 -6.5 0 0 0.2 0.2 {} diff --git a/xschem_library/generators/schematicgen b/xschem_library/generators/schematicgen new file mode 100755 index 00000000..e9553761 --- /dev/null +++ b/xschem_library/generators/schematicgen @@ -0,0 +1,81 @@ +#!/bin/sh +# the next line restarts using wish \ +exec tclsh "$0" "$@" + +set arg1 [lindex $argv 0] +if { $arg1 eq {inv}} { +puts {v {xschem version=3.1.0 file_version=1.2} +G { +y <= not a after 0.1 ns ;} +K {} +V {assign #150 y=~a ;} +S {} +E {} +N 190 -250 190 -210 {lab=y} +N 190 -230 230 -230 {lab=y} +N 150 -280 150 -180 {lab=a} +N 110 -230 150 -230 {lab=a} +N 190 -280 270 -280 {lab=VCC} +N 270 -310 270 -280 {lab=VCC} +N 190 -310 270 -310 {lab=VCC} +N 190 -180 290 -180 {lab=0} +N 290 -180 290 -150 {lab=0} +N 190 -150 290 -150 {lab=0} +N 190 -350 190 -310 {lab=VCC} +N 190 -150 190 -130 {lab=0} +C {opin.sym} 230 -230 0 0 {name=p1 lab=y verilog_type=wire} +C {ipin.sym} 110 -230 0 0 {name=p2 lab=a} +C {p.sym} 170 -280 0 0 {name=m2 model=cmosp w=wp l=lp m=1 } +C {lab_pin.sym} 190 -350 0 0 {name=p149 lab=VCC} +C {lab_pin.sym} 190 -130 0 0 {name=p3 lab=0} +C {n.sym} 170 -180 0 0 {name=m1 model=cmosn w=wn l=lln m=1} +C {title.sym} 160 0 0 0 {name=l3 author="Stefan Schippers"} +} +} else { +puts {v {xschem version=3.1.0 file_version=1.2} +G { +y <= not a after 0.1 ns ;} +K {} +V {assign #150 y=~a ;} +S {} +E {} +N 190 -230 190 -210 {lab=y} +N 190 -230 380 -230 {lab=y} +N 150 -230 150 -180 {lab=a} +N 110 -230 150 -230 {lab=a} +N 190 -280 270 -280 {lab=VCC} +N 270 -310 270 -280 {lab=VCC} +N 190 -310 270 -310 {lab=VCC} +N 190 -180 290 -180 {lab=0} +N 290 -180 290 -150 {lab=0} +N 190 -150 290 -150 {lab=0} +N 190 -350 190 -310 {lab=VCC} +N 190 -150 190 -130 {lab=0} +N 420 -230 420 -210 {lab=y} +N 420 -230 500 -230 {lab=y} +N 380 -230 380 -180 {lab=a} +N 420 -280 500 -280 {lab=VCC} +N 500 -310 500 -280 {lab=VCC} +N 420 -310 500 -310 {lab=VCC} +N 420 -180 520 -180 {lab=0} +N 520 -180 520 -150 {lab=0} +N 420 -150 520 -150 {lab=0} +N 420 -350 420 -310 {lab=VCC} +N 420 -150 420 -130 {lab=0} +N 190 -250 190 -230 {lab=y} +N 150 -280 150 -230 {lab=a} +N 420 -250 420 -230 {lab=y} +N 380 -280 380 -230 {lab=a} +C {opin.sym} 500 -230 0 0 {name=p1 lab=y verilog_type=wire} +C {ipin.sym} 110 -230 0 0 {name=p2 lab=a} +C {p.sym} 170 -280 0 0 {name=m2 model=cmosp w=wp l=lp m=1 } +C {lab_pin.sym} 190 -350 0 0 {name=p149 lab=VCC} +C {lab_pin.sym} 190 -130 0 0 {name=p3 lab=0} +C {n.sym} 170 -180 0 0 {name=m1 model=cmosn w=wn l=lln m=1} +C {title.sym} 160 0 0 0 {name=l3 author="Stefan Schippers"} +C {p.sym} 400 -280 0 0 {name=m3 model=cmosp w=wp l=lp m=1 } +C {lab_pin.sym} 420 -350 0 0 {name=p4 lab=VCC} +C {lab_pin.sym} 420 -130 0 0 {name=p5 lab=0} +C {n.sym} 400 -180 0 0 {name=m4 model=cmosn w=wn l=lln m=1} +} +} diff --git a/xschem_library/generators/symbolgen b/xschem_library/generators/symbolgen index 213e9138..874565b4 100755 --- a/xschem_library/generators/symbolgen +++ b/xschem_library/generators/symbolgen @@ -8,23 +8,23 @@ puts {v {xschem version=3.1.0 file_version=1.2} K {type=subcircuit verilog_primitive=true vhdl_primitive=true -vhdl_format="@@Y <= not @@A after 90 ps;" -verilog_format="assign #90 @@Y = ~@@A ;" -format="@name @pinlist @symname ROUT=@ROUT" -template="name=x1 ROUT=1000" -schematic=inv_ngspice.sch} +vhdl_format="@@y <= not @@a after 90 ps;" +verilog_format="assign #90 @@y = ~@@a ;" +format="@name @pinlist @symname wn=@wn lln=@lln wp=@wp lp=@lp" +template="name=x1 wn=1u lln=2u wp=4u lp=2u" +schematic=schematicgen(inv)} L 4 -40 0 -20 0 {} L 4 -20 -20 20 0 {} L 4 -20 -20 -20 20 {} L 4 -20 20 20 0 {} L 4 30 -0 40 -0 {} -B 5 37.5 -2.5 42.5 2.5 {name=Y dir=out } -B 5 -42.5 -2.5 -37.5 2.5 {name=A dir=in } +B 5 37.5 -2.5 42.5 2.5 {name=y dir=out } +B 5 -42.5 -2.5 -37.5 2.5 {name=a dir=in } A 4 25 -0 5 180 360 {} T {@symname} -47.5 24 0 0 0.3 0.3 {} T {@name} 25 -22 0 0 0.2 0.2 {} -T {Y} 7.5 -6.5 0 1 0.2 0.2 {} -T {A} -17.5 -6.5 0 0 0.2 0.2 {} +T {y} 7.5 -6.5 0 1 0.2 0.2 {} +T {a} -17.5 -6.5 0 0 0.2 0.2 {} T {ROUT=@ROUT} -25 -42 0 0 0.2 0.2 {} } } else { @@ -32,22 +32,22 @@ puts {v {xschem version=3.1.0 file_version=1.2} K {type=subcircuit verilog_primitive=true vhdl_primitive=true -vhdl_format="@@Y <= @@A after 90 ps;" -verilog_format="assign #90 @@Y = @@A ;" -format="@name @pinlist @symname ROUT=@ROUT" -template="name=x1 ROUT=1000" -schematic=buf_ngspice.sch} +vhdl_format="@@y <= @@a after 90 ps;" +verilog_format="assign #90 @@y = @@a ;" +format="@name @pinlist @symname wn=@wn lln=@lln wp=@wp lp=@lp" +template="name=x1 wn=1u lln=2u wp=4u lp=2u" +schematic=schematicgen(buf)} L 4 20 0 40 0 {} L 4 -40 0 -20 0 {} L 4 -20 -20 20 0 {} L 4 -20 -20 -20 20 {} L 4 -20 20 20 0 {} -B 5 37.5 -2.5 42.5 2.5 {name=Y dir=out } -B 5 -42.5 -2.5 -37.5 2.5 {name=A dir=in } +B 5 37.5 -2.5 42.5 2.5 {name=y dir=out } +B 5 -42.5 -2.5 -37.5 2.5 {name=a dir=in } T {@symname} -47.5 24 0 0 0.3 0.3 {} T {@name} 25 -22 0 0 0.2 0.2 {} -T {Y} 7.5 -6.5 0 1 0.2 0.2 {} -T {A} -17.5 -6.5 0 0 0.2 0.2 {} +T {y} 7.5 -6.5 0 1 0.2 0.2 {} +T {a} -17.5 -6.5 0 0 0.2 0.2 {} T {ROUT=@ROUT} -25 -42 0 0 0.2 0.2 {} } } diff --git a/xschem_library/generators/test_symbolgen.sch b/xschem_library/generators/test_symbolgen.sch index dc3e2f8e..8f784f50 100644 --- a/xschem_library/generators/test_symbolgen.sch +++ b/xschem_library/generators/test_symbolgen.sch @@ -7,20 +7,22 @@ S {} E {} B 2 560 -400 1170 -150 {flags=graph y1=0 -y2=2 -ypos1=-0.0262499 -ypos2=0.9491 +y2=3 +ypos1=0.157569 +ypos2=1.98753 divy=5 subdivy=1 unity=1 -x1=5.80963e-09 -x2=2.34017e-08 +x1=1e-11 +x2=3e-07 divx=5 subdivx=1 node="in in_inv -in_buf" -color="7 4 8" +in_buf +in_inv2 +in_buf2" +color="7 4 8 9 10" dataset=-1 unitx=1 logx=0 @@ -42,6 +44,16 @@ N 230 -250 350 -250 { lab=IN_BUF} N 230 -120 350 -120 { lab=IN_INV} +N 600 -470 630 -470 { +lab=IN} +N 710 -470 740 -470 { +lab=IN_INV2} +N 890 -470 920 -470 { +lab=IN} +N 1000 -470 1030 -470 { +lab=IN_BUF2} +N 500 -310 500 -280 { +lab=VCC} C {symbolgen(inv)} 190 -120 0 0 {name=x1 tclcommand="edit_file [abs_sym_path symbolgen]" ROUT=1200} @@ -55,12 +67,13 @@ C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"} C {code_shown.sym} 40 -540 0 0 {name=CONTROL tclcommand="xschem edit_vi_prop" xxplace=end -value=" -.param vcc=1.8 -Vin in 0 pwl 0 0 10n 0 10.1n 1.8 20n 1.8 20.1n 0 +value=".include models_rom8k.txt +.param vcc=3 +vvcc vcc 0 dc 3 +Vin in 0 pwl 0 0 100n 0 100.1n 3 200n 3 200.1n 0 .control save all - tran 0.2n 30n uic + tran 1n 300n uic write test_symbolgen.raw .endc "} @@ -70,3 +83,13 @@ C {launcher.sym} 620 -130 0 0 {name=h5 descr="load waves" tclcommand="xschem raw_read $netlist_dir/test_symbolgen.raw tran" } +C {my_inv.sym} 670 -470 0 0 {name=x2 ROUT=1000 +schematic=schematicgen(inv)} +C {lab_pin.sym} 600 -470 0 0 {name=p4 lab=IN} +C {lab_pin.sym} 740 -470 0 1 {name=p5 lab=IN_INV2} +C {my_inv.sym} 960 -470 0 0 {name=x4 ROUT=1000 +schematic=schematicgen(buf)} +C {lab_pin.sym} 890 -470 0 0 {name=p6 lab=IN} +C {lab_pin.sym} 1030 -470 0 1 {name=p7 lab=IN_BUF2} +C {vdd.sym} 500 -310 0 0 {name=l2 lab=VCC} +C {lab_pin.sym} 500 -280 0 1 {name=p8 lab=VCC}